diff options
Diffstat (limited to 'src/arch/power/tlb.cc')
| -rw-r--r-- | src/arch/power/tlb.cc | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/src/arch/power/tlb.cc b/src/arch/power/tlb.cc index ff2f94fb6..703b92e2b 100644 --- a/src/arch/power/tlb.cc +++ b/src/arch/power/tlb.cc @@ -145,7 +145,7 @@ TLB::probeEntry(Addr vpn,uint8_t asn) const } inline Fault -TLB::checkCacheability(RequestPtr &req) +TLB::checkCacheability(const RequestPtr &req) { Addr VAddrUncacheable = 0xA0000000; if ((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) { @@ -279,7 +279,7 @@ TLB::regStats() } Fault -TLB::translateInst(RequestPtr req, ThreadContext *tc) +TLB::translateInst(const RequestPtr &req, ThreadContext *tc) { // Instruction accesses must be word-aligned if (req->getVaddr() & 0x3) { @@ -298,7 +298,7 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc) } Fault -TLB::translateData(RequestPtr req, ThreadContext *tc, bool write) +TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write) { Process * p = tc->getProcessPtr(); @@ -310,7 +310,7 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write) } Fault -TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) +TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode) { if (FullSystem) fatal("translate atomic not yet implemented in full system mode.\n"); @@ -322,7 +322,7 @@ TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) } void -TLB::translateTiming(RequestPtr req, ThreadContext *tc, +TLB::translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode) { assert(translation); @@ -330,7 +330,8 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc, } Fault -TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const +TLB::finalizePhysical(const RequestPtr &req, + ThreadContext *tc, Mode mode) const { return NoFault; } |