12 files changed, 444 insertions, 14 deletions
diff --git a/src/arch/power/PowerInterrupts.py b/src/arch/power/PowerInterrupts.py
new file mode 100644
index 000000000..82d614077
--- /dev/null
+++ b/src/arch/power/PowerInterrupts.py
@@ -0,0 +1,33 @@
+# Copyright (c) 2011 Google
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+from m5.SimObject import SimObject
+
+class PowerInterrupts(SimObject):
+    type = 'PowerInterrupts'
+    cxx_class = 'PowerISA::Interrupts'
diff --git a/src/arch/power/SConscript b/src/arch/power/SConscript
index f96f12757..7f893ca37 100644
--- a/src/arch/power/SConscript
+++ b/src/arch/power/SConscript
@@ -40,17 +40,20 @@ if env['TARGET_ISA'] == 'power':
     Source('insts/floating.cc')
     Source('insts/condition.cc')
     Source('insts/static_inst.cc')
+    Source('interrupts.cc')
+    Source('linux/linux.cc')
+    Source('linux/process.cc')
     Source('pagetable.cc')
+    Source('process.cc')
+    Source('stacktrace.cc')
     Source('tlb.cc')
     Source('utility.cc')
+    Source('vtophys.cc')
 
+    SimObject('PowerInterrupts.py')
     SimObject('PowerTLB.py')
-    DebugFlag('Power')
 
-    if not env['FULL_SYSTEM']:
-        Source('process.cc')
-        Source('linux/linux.cc')
-        Source('linux/process.cc')
+    DebugFlag('Power')
 
     # Add in files generated by the ISA description.
     isa_desc_files = env.ISADesc('isa/main.isa')
diff --git a/src/arch/power/interrupts.cc b/src/arch/power/interrupts.cc
new file mode 100644
index 000000000..c9ef36824
--- /dev/null
+++ b/src/arch/power/interrupts.cc
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2011 Google
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/power/interrupts.hh"
+
+PowerISA::Interrupts *
+PowerInterruptsParams::create()
+{
+    return new PowerISA::Interrupts(this);
+}
diff --git a/src/arch/power/interrupts.hh b/src/arch/power/interrupts.hh
new file mode 100644
index 000000000..9c11c8e8a
--- /dev/null
+++ b/src/arch/power/interrupts.hh
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2011 Google
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_POWER_INTERRUPT_HH__
+#define __ARCH_POWER_INTERRUPT_HH__
+
+#include "base/misc.hh"
+#include "params/PowerInterrupts.hh"
+#include "sim/sim_object.hh"
+
+class ThreadContext;
+
+namespace PowerISA {
+
+class Interrupts : public SimObject
+{
+  private:
+    BaseCPU * cpu;
+
+  public:
+    typedef PowerInterruptsParams Params;
+
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
+
+    Interrupts(Params * p) : SimObject(p), cpu(NULL)
+    {}
+
+    void
+    setCPU(BaseCPU * _cpu)
+    {
+        cpu = _cpu;
+    }
+
+    void
+    post(int int_num, int index)
+    {
+        panic("Interrupts::post not implemented.\n");
+    }
+
+    void
+    clear(int int_num, int index)
+    {
+        panic("Interrupts::clear not implemented.\n");
+    }
+
+    void
+    clearAll()
+    {
+        panic("Interrupts::clearAll not implemented.\n");
+    }
+
+    bool
+    checkInterrupts(ThreadContext *tc) const
+    {
+        panic("Interrupts::checkInterrupts not implemented.\n");
+    }
+
+    Fault
+    getInterrupt(ThreadContext *tc)
+    {
+        panic("Interrupts::getInterrupt not implemented.\n");
+    }
+
+    void
+    updateIntrInfo(ThreadContext *tc)
+    {
+        panic("Interrupts::updateIntrInfo not implemented.\n");
+    }
+};
+
+} // namespace PowerISA
+
+#endif // __ARCH_POWER_INTERRUPT_HH__
+
diff --git a/src/arch/power/kernel_stats.hh b/src/arch/power/kernel_stats.hh
new file mode 100644
index 000000000..b4d9a69b6
--- /dev/null
+++ b/src/arch/power/kernel_stats.hh
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_POWER_KERNEL_STATS_HH__
+#define __ARCH_POWER_KERNEL_STATS_HH__
+
+#include "kern/kernel_stats.hh"
+
+namespace PowerISA {
+namespace Kernel {
+
+enum cpu_mode { hypervisor, kernel, user, idle, cpu_mode_num };
+extern const char *modestr[];
+
+class Statistics : public ::Kernel::Statistics
+{
+  public:
+    Statistics(System *system) : ::Kernel::Statistics(system)
+    {}
+};
+
+} // namespace PowerISA::Kernel
+} // namespace PowerISA
+
+#endif // __ARCH_POWER_KERNEL_STATS_HH__
diff --git a/src/arch/power/pagetable.hh b/src/arch/power/pagetable.hh
index a5f18eba9..3097aa526 100644
--- a/src/arch/power/pagetable.hh
+++ b/src/arch/power/pagetable.hh
@@ -41,7 +41,6 @@
 #include "arch/power/isa_traits.hh"
 #include "arch/power/utility.hh"
 #include "arch/power/vtophys.hh"
-#include "config/full_system.hh"
 
 namespace PowerISA {
 
diff --git a/src/arch/power/stacktrace.cc b/src/arch/power/stacktrace.cc
new file mode 100644
index 000000000..5fcb6342c
--- /dev/null
+++ b/src/arch/power/stacktrace.cc
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ */
+
+#include <string>
+
+#include "arch/power/stacktrace.hh"
+#include "base/trace.hh"
+
+using namespace std;
+
+namespace PowerISA {
+
+ProcessInfo::ProcessInfo(ThreadContext *_tc)
+    : tc(_tc)
+{
+    panic("ProcessInfo constructor not implemented.\n");
+}
+
+Addr
+ProcessInfo::task(Addr ksp) const
+{
+    panic("ProcessInfo::task not implemented.\n");
+    return 0;
+}
+
+int
+ProcessInfo::pid(Addr ksp) const
+{
+    panic("ProcessInfo::pid not implemented.\n");
+    return 0;
+}
+
+string
+ProcessInfo::name(Addr ksp) const
+{
+    panic("ProcessInfo::name not implemented.\n");
+    return "";
+}
+
+StackTrace::StackTrace()
+    : tc(0), stack(64)
+{
+    panic("StackTrace constructor not implemented.\n");
+}
+
+StackTrace::StackTrace(ThreadContext *_tc, StaticInstPtr inst)
+    : tc(0), stack(64)
+{
+    panic("StackTrace constructor not implemented.\n");
+}
+
+StackTrace::~StackTrace()
+{
+    panic("StackTrace destructor not implemented.\n");
+}
+
+void
+StackTrace::trace(ThreadContext *_tc, bool is_call)
+{
+    panic("StackTrace::trace not implemented.\n");
+}
+
+bool
+StackTrace::isEntry(Addr addr)
+{
+    panic("StackTrace::isEntry not implemented.\n");
+    return false;
+}
+
+bool
+StackTrace::decodeStack(MachInst inst, int &disp)
+{
+    panic("StackTrace::decodeStack not implemented.\n");
+    return false;
+}
+
+bool
+StackTrace::decodeSave(MachInst inst, int &reg, int &disp)
+{
+    panic("StackTrace::decodeSave not implemented.\n");
+    return true;
+}
+
+/*
+ * Decode the function prologue for the function we're in, and note
+ * which registers are stored where, and how large the stack frame is.
+ */
+bool
+StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func, int &size,
+                           Addr &ra)
+{
+    panic("StackTrace::decodePrologue not implemented.\n");
+    return true;
+}
+
+#if TRACING_ON
+void
+StackTrace::dump()
+{
+    panic("StackTrace::dump not implemented.\n");
+}
+#endif
+
+} // namespace PowerISA
diff --git a/src/arch/power/tlb.cc b/src/arch/power/tlb.cc
index 0b3edd5a2..2148e875a 100644
--- a/src/arch/power/tlb.cc
+++ b/src/arch/power/tlb.cc
@@ -50,6 +50,7 @@
 #include "debug/TLB.hh"
 #include "mem/page_table.hh"
 #include "params/PowerTLB.hh"
+#include "sim/full_system.hh"
 #include "sim/process.hh"
 
 using namespace std;
@@ -308,14 +309,14 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
 Fault
 TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
 {
-#if !FULL_SYSTEM
-    if (mode == Execute)
-        return translateInst(req, tc);
-    else
-        return translateData(req, tc, mode == Write);
-#else
-  fatal("translate atomic not yet implemented\n");
-#endif
+    if (FullSystem) {
+        fatal("translate atomic not yet implemented in full system mode.\n");
+    } else {
+        if (mode == Execute)
+            return translateInst(req, tc);
+        else
+            return translateData(req, tc, mode == Write);
+    }
 }
 
 void
diff --git a/src/arch/power/utility.cc b/src/arch/power/utility.cc
index b02ccda08..e3fa246fc 100644
--- a/src/arch/power/utility.cc
+++ b/src/arch/power/utility.cc
@@ -55,11 +55,24 @@ copyRegs(ThreadContext *src, ThreadContext *dest)
     dest->pcState(src->pcState());
 }
 
+uint64_t
+getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
+{
+    panic("getArgument not implemented for POWER.\n");
+    return 0;
+}
+
 void
 skipFunction(ThreadContext *tc)
 {
     panic("Not Implemented for POWER");
 }
 
+void
+initCPU(ThreadContext *tc, int cpuId)
+{
+    panic("initCPU not implemented for POWER.\n");
+}
+
 
 } // namespace PowerISA
diff --git a/src/arch/power/utility.hh b/src/arch/power/utility.hh
index 349054774..c3868c189 100644
--- a/src/arch/power/utility.hh
+++ b/src/arch/power/utility.hh
@@ -78,6 +78,8 @@ advancePC(PCState &pc, const StaticInstPtr inst)
     pc.advance();
 }
 
+uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
+
 static inline bool
 inUserMode(ThreadContext *tc)
 {
@@ -90,6 +92,8 @@ getExecutingAsid(ThreadContext *tc)
     return 0;
 }
 
+void initCPU(ThreadContext *, int cpuId);
+
 } // namespace PowerISA
 
 
diff --git a/src/arch/power/vtophys.cc b/src/arch/power/vtophys.cc
new file mode 100755
index 000000000..597f41b2f
--- /dev/null
+++ b/src/arch/power/vtophys.cc
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * Copyright (c) 2007 MIPS Technologies, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ *          Nathan Binkert
+ *          Jaidev Patwardhan
+ */
+
+#include "arch/power/vtophys.hh"
+
+using namespace std;
+
+Addr
+PowerISA::vtophys(Addr vaddr)
+{
+    fatal("VTOPHYS: Unimplemented on POWER\n");
+}
+
+Addr
+PowerISA::vtophys(ThreadContext *tc, Addr addr)
+{
+    fatal("VTOPHYS: Unimplemented on POWER\n");
+}
+
diff --git a/src/arch/power/vtophys.hh b/src/arch/power/vtophys.hh
index 7371f38a6..a2582b296 100644
--- a/src/arch/power/vtophys.hh
+++ b/src/arch/power/vtophys.hh
@@ -44,6 +44,9 @@ class FunctionalPort;
 
 namespace PowerISA {
 
+Addr vtophys(Addr vaddr);
+Addr vtophys(ThreadContext *tc, Addr vaddr);
+
 inline Addr
 PteAddr(Addr a)
 {