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-rw-r--r--src/arch/power/faults.hh2
-rw-r--r--src/arch/power/insts/branch.hh2
-rw-r--r--src/arch/power/insts/condition.hh2
-rw-r--r--src/arch/power/insts/floating.hh2
-rw-r--r--src/arch/power/insts/integer.hh2
-rw-r--r--src/arch/power/insts/mem.hh2
-rw-r--r--src/arch/power/insts/misc.hh2
-rw-r--r--src/arch/power/insts/static_inst.hh2
-rw-r--r--src/arch/power/isa.hh2
-rw-r--r--src/arch/power/isa_traits.hh4
-rw-r--r--src/arch/power/locked_mem.hh2
-rw-r--r--src/arch/power/microcode_rom.hh2
-rw-r--r--src/arch/power/miscregs.hh2
-rw-r--r--src/arch/power/mmaped_ipr.hh2
-rw-r--r--src/arch/power/pagetable.cc2
-rw-r--r--src/arch/power/pagetable.hh2
-rw-r--r--src/arch/power/predecoder.hh2
-rw-r--r--src/arch/power/registers.hh2
-rw-r--r--src/arch/power/remote_gdb.hh2
-rw-r--r--src/arch/power/stacktrace.hh2
-rw-r--r--src/arch/power/tlb.hh2
-rw-r--r--src/arch/power/types.hh2
-rw-r--r--src/arch/power/utility.cc2
-rw-r--r--src/arch/power/utility.hh2
-rw-r--r--src/arch/power/vtophys.hh2
25 files changed, 26 insertions, 26 deletions
diff --git a/src/arch/power/faults.hh b/src/arch/power/faults.hh
index 0f49cc85d..f1977150c 100644
--- a/src/arch/power/faults.hh
+++ b/src/arch/power/faults.hh
@@ -98,6 +98,6 @@ genMachineCheckFault()
return new MachineCheckFault();
}
-} // PowerISA namespace
+} // namespace PowerISA
#endif // __ARCH_POWER_FAULTS_HH__
diff --git a/src/arch/power/insts/branch.hh b/src/arch/power/insts/branch.hh
index 7b9e78dee..1947e4ec3 100644
--- a/src/arch/power/insts/branch.hh
+++ b/src/arch/power/insts/branch.hh
@@ -236,6 +236,6 @@ class BranchRegCond : public BranchCond
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
-} // PowerISA namespace
+} // namespace PowerISA
#endif //__ARCH_POWER_INSTS_BRANCH_HH__
diff --git a/src/arch/power/insts/condition.hh b/src/arch/power/insts/condition.hh
index a23667d9e..e5112b2c1 100644
--- a/src/arch/power/insts/condition.hh
+++ b/src/arch/power/insts/condition.hh
@@ -81,6 +81,6 @@ class CondMoveOp : public PowerStaticInst
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
-} // PowerISA namespace
+} // namespace PowerISA
#endif //__ARCH_POWER_INSTS_CONDITION_HH__
diff --git a/src/arch/power/insts/floating.hh b/src/arch/power/insts/floating.hh
index 2b2668409..deeac82cf 100644
--- a/src/arch/power/insts/floating.hh
+++ b/src/arch/power/insts/floating.hh
@@ -148,6 +148,6 @@ class FloatOp : public PowerStaticInst
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
-} // PowerISA namespace
+} // namespace PowerISA
#endif //__ARCH_POWER_INSTS_FLOATING_HH__
diff --git a/src/arch/power/insts/integer.hh b/src/arch/power/insts/integer.hh
index b4b96d5dc..a7270cd38 100644
--- a/src/arch/power/insts/integer.hh
+++ b/src/arch/power/insts/integer.hh
@@ -171,6 +171,6 @@ class IntRotateOp : public IntShiftOp
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
-} // PowerISA namespace
+} // namespace PowerISA
#endif //__ARCH_POWER_INSTS_INTEGER_HH__
diff --git a/src/arch/power/insts/mem.hh b/src/arch/power/insts/mem.hh
index 329dafe57..a58742690 100644
--- a/src/arch/power/insts/mem.hh
+++ b/src/arch/power/insts/mem.hh
@@ -86,6 +86,6 @@ class MemDispOp : public MemOp
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
-} // PowerISA namespace
+} // namespace PowerISA
#endif //__ARCH_POWER_INSTS_MEM_HH__
diff --git a/src/arch/power/insts/misc.hh b/src/arch/power/insts/misc.hh
index dd4941b93..d6a73d254 100644
--- a/src/arch/power/insts/misc.hh
+++ b/src/arch/power/insts/misc.hh
@@ -52,6 +52,6 @@ class MiscOp : public PowerStaticInst
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
-} // PowerISA namespace
+} // namespace PowerISA
#endif //__ARCH_POWER_INSTS_MISC_HH__
diff --git a/src/arch/power/insts/static_inst.hh b/src/arch/power/insts/static_inst.hh
index 91eca6fb0..48e5fa94b 100644
--- a/src/arch/power/insts/static_inst.hh
+++ b/src/arch/power/insts/static_inst.hh
@@ -71,6 +71,6 @@ class PowerStaticInst : public StaticInst
}
};
-} // PowerISA namespace
+} // namespace PowerISA
#endif //__ARCH_POWER_INSTS_STATICINST_HH__
diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh
index ba1b5018d..78ae18ea9 100644
--- a/src/arch/power/isa.hh
+++ b/src/arch/power/isa.hh
@@ -110,6 +110,6 @@ class ISA
}
};
-} // PowerISA namespace
+} // namespace PowerISA
#endif // __ARCH_POWER_ISA_HH__
diff --git a/src/arch/power/isa_traits.hh b/src/arch/power/isa_traits.hh
index ab6a56760..f0f50b9e9 100644
--- a/src/arch/power/isa_traits.hh
+++ b/src/arch/power/isa_traits.hh
@@ -38,7 +38,7 @@
#include "arch/power/types.hh"
#include "base/types.hh"
-namespace BigEndianGuest {};
+namespace BigEndianGuest {}
class StaticInstPtr;
@@ -73,6 +73,6 @@ const ExtMachInst NoopMachInst = 0x60000000;
// Memory accesses can be unaligned
const bool HasUnalignedMemAcc = true;
-} // PowerISA namespace
+} // namespace PowerISA
#endif // __ARCH_POWER_ISA_TRAITS_HH__
diff --git a/src/arch/power/locked_mem.hh b/src/arch/power/locked_mem.hh
index 56ab1d4a0..6141b9ef2 100644
--- a/src/arch/power/locked_mem.hh
+++ b/src/arch/power/locked_mem.hh
@@ -59,6 +59,6 @@ handleLockedWrite(XC *xc, Request *req)
return true;
}
-} // PowerISA namespace
+} // namespace PowerISA
#endif // __ARCH_POWER_LOCKED_MEM_HH__
diff --git a/src/arch/power/microcode_rom.hh b/src/arch/power/microcode_rom.hh
index e35db5112..0cb100653 100644
--- a/src/arch/power/microcode_rom.hh
+++ b/src/arch/power/microcode_rom.hh
@@ -40,6 +40,6 @@ namespace PowerISA
using ::MicrocodeRom;
-} // PowerISA namespace
+} // namespace PowerISA
#endif // __ARCH_POWER_MICROCODE_ROM_HH__
diff --git a/src/arch/power/miscregs.hh b/src/arch/power/miscregs.hh
index 34732dad1..eba97d439 100644
--- a/src/arch/power/miscregs.hh
+++ b/src/arch/power/miscregs.hh
@@ -95,6 +95,6 @@ BitUnion32(Fpscr)
Bitfield<2,1> rn;
EndBitUnion(Fpscr)
-}; // PowerISA namespace
+} // namespace PowerISA
#endif // __ARCH_POWER_MISCREGS_HH__
diff --git a/src/arch/power/mmaped_ipr.hh b/src/arch/power/mmaped_ipr.hh
index bd1ea10b3..fc88634dc 100644
--- a/src/arch/power/mmaped_ipr.hh
+++ b/src/arch/power/mmaped_ipr.hh
@@ -61,6 +61,6 @@ handleIprWrite(ThreadContext *xc, Packet *pkt)
panic("No implementation for handleIprWrite in POWER\n");
}
-} // PowerISA namespace
+} // namespace PowerISA
#endif // __ARCH_POWER_MMAPED_IPR_HH__
diff --git a/src/arch/power/pagetable.cc b/src/arch/power/pagetable.cc
index 862404578..091fb8bc8 100644
--- a/src/arch/power/pagetable.cc
+++ b/src/arch/power/pagetable.cc
@@ -79,4 +79,4 @@ PTE::unserialize(Checkpoint *cp, const std::string &section)
UNSERIALIZE_SCALAR(OffsetMask);
}
-} // PowerISA namespace
+} // namespace PowerISA
diff --git a/src/arch/power/pagetable.hh b/src/arch/power/pagetable.hh
index bd2b9d397..a5f18eba9 100644
--- a/src/arch/power/pagetable.hh
+++ b/src/arch/power/pagetable.hh
@@ -152,7 +152,7 @@ struct PTE
void unserialize(Checkpoint *cp, const std::string &section);
};
-} // PowerISA namespace
+} // namespace PowerISA
#endif // __ARCH_POWER_PAGETABLE_H__
diff --git a/src/arch/power/predecoder.hh b/src/arch/power/predecoder.hh
index 431c5d1b7..8b1089095 100644
--- a/src/arch/power/predecoder.hh
+++ b/src/arch/power/predecoder.hh
@@ -120,6 +120,6 @@ class Predecoder
}
};
-} // PowerISA namespace
+} // namespace PowerISA
#endif // __ARCH_POWER_PREDECODER_HH__
diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index 59816a599..8b2aefc47 100644
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -101,6 +101,6 @@ enum MiscIntRegNums {
INTREG_RSV_ADDR
};
-} // PowerISA namespace
+} // namespace PowerISA
#endif // __ARCH_POWER_REGISTERS_HH__
diff --git a/src/arch/power/remote_gdb.hh b/src/arch/power/remote_gdb.hh
index 34bb4bd1f..b37c31713 100644
--- a/src/arch/power/remote_gdb.hh
+++ b/src/arch/power/remote_gdb.hh
@@ -79,6 +79,6 @@ class RemoteGDB : public BaseRemoteGDB
}
};
-} // PowerISA namespace
+} // namespace PowerISA
#endif /* __ARCH_POWER_REMOTE_GDB_H__ */
diff --git a/src/arch/power/stacktrace.hh b/src/arch/power/stacktrace.hh
index 49d687a6e..e87203df6 100644
--- a/src/arch/power/stacktrace.hh
+++ b/src/arch/power/stacktrace.hh
@@ -143,6 +143,6 @@ StackTrace::trace(ThreadContext *tc, StaticInstPtr inst)
return true;
}
-} // PowerISA namespace
+} // namespace PowerISA
#endif // __ARCH_POWER_STACKTRACE_HH__
diff --git a/src/arch/power/tlb.hh b/src/arch/power/tlb.hh
index 8431b9ad1..7e5638cf1 100644
--- a/src/arch/power/tlb.hh
+++ b/src/arch/power/tlb.hh
@@ -167,6 +167,6 @@ class TLB : public BaseTLB
void regStats();
};
-} // PowerISA namespace
+} // namespace PowerISA
#endif // __ARCH_POWER_TLB_HH__
diff --git a/src/arch/power/types.hh b/src/arch/power/types.hh
index d049cdec1..61f8acfca 100644
--- a/src/arch/power/types.hh
+++ b/src/arch/power/types.hh
@@ -101,6 +101,6 @@ struct hash<PowerISA::ExtMachInst> : public hash<uint32_t> {
};
};
-} // __hash_namespace namespace
+} // namespace __hash_namespace
#endif // __ARCH_POWER_TYPES_HH__
diff --git a/src/arch/power/utility.cc b/src/arch/power/utility.cc
index 399ec1f56..b02ccda08 100644
--- a/src/arch/power/utility.cc
+++ b/src/arch/power/utility.cc
@@ -62,4 +62,4 @@ skipFunction(ThreadContext *tc)
}
-} // PowerISA namespace
+} // namespace PowerISA
diff --git a/src/arch/power/utility.hh b/src/arch/power/utility.hh
index a47fcdc46..cbb9bb646 100644
--- a/src/arch/power/utility.hh
+++ b/src/arch/power/utility.hh
@@ -78,6 +78,6 @@ advancePC(PCState &pc, const StaticInstPtr inst)
pc.advance();
}
-} // PowerISA namespace
+} // namespace PowerISA
#endif // __ARCH_POWER_UTILITY_HH__
diff --git a/src/arch/power/vtophys.hh b/src/arch/power/vtophys.hh
index 3cfebcfc7..8b88c9215 100644
--- a/src/arch/power/vtophys.hh
+++ b/src/arch/power/vtophys.hh
@@ -51,7 +51,7 @@ PteAddr(Addr a)
return (a & PteMask) << PteShift;
}
-} // PowerISA namespace
+} // namespace PowerISA
#endif // __ARCH_POWER_VTOPHYS_HH__
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-05 12:14:55 +0000