diff options
Diffstat (limited to 'src/arch/power')
-rw-r--r-- | src/arch/power/insts/branch.cc | 24 | ||||
-rw-r--r-- | src/arch/power/insts/branch.hh | 10 | ||||
-rw-r--r-- | src/arch/power/insts/static_inst.hh | 6 | ||||
-rw-r--r-- | src/arch/power/isa/decoder.isa | 36 | ||||
-rw-r--r-- | src/arch/power/isa/formats/branch.isa | 6 | ||||
-rw-r--r-- | src/arch/power/isa/formats/unknown.isa | 2 | ||||
-rw-r--r-- | src/arch/power/isa/operands.isa | 3 | ||||
-rw-r--r-- | src/arch/power/predecoder.hh | 4 | ||||
-rw-r--r-- | src/arch/power/process.cc | 4 | ||||
-rw-r--r-- | src/arch/power/types.hh | 3 | ||||
-rw-r--r-- | src/arch/power/utility.cc | 3 | ||||
-rw-r--r-- | src/arch/power/utility.hh | 15 |
12 files changed, 80 insertions, 36 deletions
diff --git a/src/arch/power/insts/branch.cc b/src/arch/power/insts/branch.cc index c10f7c996..352c4ea57 100644 --- a/src/arch/power/insts/branch.cc +++ b/src/arch/power/insts/branch.cc @@ -52,10 +52,10 @@ PCDependentDisassembly::disassemble(Addr pc, const SymbolTable *symtab) const return *cachedDisassembly; } -Addr -BranchPCRel::branchTarget(Addr pc) const +PowerISA::PCState +BranchPCRel::branchTarget(const PowerISA::PCState &pc) const { - return (uint32_t)(pc + disp); + return (uint32_t)(pc.pc() + disp); } std::string @@ -76,8 +76,8 @@ BranchPCRel::generateDisassembly(Addr pc, const SymbolTable *symtab) const return ss.str(); } -Addr -BranchNonPCRel::branchTarget(Addr pc) const +PowerISA::PCState +BranchNonPCRel::branchTarget(const PowerISA::PCState &pc) const { return targetAddr; } @@ -98,10 +98,10 @@ BranchNonPCRel::generateDisassembly(Addr pc, const SymbolTable *symtab) const return ss.str(); } -Addr -BranchPCRelCond::branchTarget(Addr pc) const +PowerISA::PCState +BranchPCRelCond::branchTarget(const PowerISA::PCState &pc) const { - return (uint32_t)(pc + disp); + return (uint32_t)(pc.pc() + disp); } std::string @@ -124,8 +124,8 @@ BranchPCRelCond::generateDisassembly(Addr pc, const SymbolTable *symtab) const return ss.str(); } -Addr -BranchNonPCRelCond::branchTarget(Addr pc) const +PowerISA::PCState +BranchNonPCRelCond::branchTarget(const PowerISA::PCState &pc) const { return targetAddr; } @@ -149,11 +149,11 @@ BranchNonPCRelCond::generateDisassembly(Addr pc, return ss.str(); } -Addr +PowerISA::PCState BranchRegCond::branchTarget(ThreadContext *tc) const { uint32_t regVal = tc->readIntReg(_srcRegIdx[_numSrcRegs - 1]); - return (regVal & 0xfffffffc); + return regVal & 0xfffffffc; } std::string diff --git a/src/arch/power/insts/branch.hh b/src/arch/power/insts/branch.hh index dd00e42c3..7b9e78dee 100644 --- a/src/arch/power/insts/branch.hh +++ b/src/arch/power/insts/branch.hh @@ -86,7 +86,7 @@ class BranchPCRel : public PCDependentDisassembly } } - Addr branchTarget(Addr pc) const; + PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; @@ -112,7 +112,7 @@ class BranchNonPCRel : public PCDependentDisassembly } } - Addr branchTarget(Addr pc) const; + PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; @@ -187,7 +187,7 @@ class BranchPCRelCond : public BranchCond } } - Addr branchTarget(Addr pc) const; + PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; @@ -213,7 +213,7 @@ class BranchNonPCRelCond : public BranchCond } } - Addr branchTarget(Addr pc) const; + PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; @@ -231,7 +231,7 @@ class BranchRegCond : public BranchCond { } - Addr branchTarget(ThreadContext *tc) const; + PowerISA::PCState branchTarget(ThreadContext *tc) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; diff --git a/src/arch/power/insts/static_inst.hh b/src/arch/power/insts/static_inst.hh index 399e75371..91eca6fb0 100644 --- a/src/arch/power/insts/static_inst.hh +++ b/src/arch/power/insts/static_inst.hh @@ -63,6 +63,12 @@ class PowerStaticInst : public StaticInst std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + + void + advancePC(PowerISA::PCState &pcState) const + { + pcState.advance(); + } }; } // PowerISA namespace diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa index 3252ff14a..671f57389 100644 --- a/src/arch/power/isa/decoder.isa +++ b/src/arch/power/isa/decoder.isa @@ -381,12 +381,20 @@ decode OPCODE default Unknown::unknown() { // Conditionally branch relative to PC based on CR and CTR. format BranchPCRelCondCtr { - 0: bc({{ NPC = PC + disp; }}); + 0: bc({{ + PowerISA::PCState pc = PCS; + pc.npc((uint32_t)(pc.pc() + disp)); + PCS = pc; + }}); } // Conditionally branch to fixed address based on CR and CTR. format BranchNonPCRelCondCtr { - 1: bca({{ NPC = targetAddr; }}); + 1: bca({{ + PowerISA::PCState pc = PCS; + pc.npc(targetAddr); + PCS = pc; + }}); } } @@ -394,12 +402,20 @@ decode OPCODE default Unknown::unknown() { // Unconditionally branch relative to PC. format BranchPCRel { - 0: b({{ NPC = PC + disp; }}); + 0: b({{ + PowerISA::PCState pc = PCS; + pc.npc((uint32_t)(pc.pc() + disp)); + PCS = pc; + }}); } // Unconditionally branch to fixed address. format BranchNonPCRel { - 1: ba({{ NPC = targetAddr; }}); + 1: ba({{ + PowerISA::PCState pc = PCS; + pc.npc(targetAddr); + PCS = pc; + }}); } } @@ -407,12 +423,20 @@ decode OPCODE default Unknown::unknown() { // Conditionally branch to address in LR based on CR and CTR. format BranchLrCondCtr { - 16: bclr({{ NPC = LR & 0xfffffffc; }}); + 16: bclr({{ + PowerISA::PCState pc = PCS; + pc.npc(LR & 0xfffffffc); + PCS = pc; + }}); } // Conditionally branch to address in CTR based on CR. format BranchCtrCond { - 528: bcctr({{ NPC = CTR & 0xfffffffc; }}); + 528: bcctr({{ + PowerISA::PCState pc = PCS; + pc.npc(CTR & 0xfffffffc); + PCS = pc; + }}); } // Condition register manipulation instructions. diff --git a/src/arch/power/isa/formats/branch.isa b/src/arch/power/isa/formats/branch.isa index d51ed5c25..da1579ea8 100644 --- a/src/arch/power/isa/formats/branch.isa +++ b/src/arch/power/isa/formats/branch.isa @@ -48,7 +48,7 @@ let {{ # Simple code to update link register (LR). -updateLrCode = 'LR = PC + 4;' +updateLrCode = 'PowerISA::PCState lrpc = PCS; LR = lrpc.pc() + 4;' }}; @@ -105,7 +105,7 @@ def GetCondCode(br_code): cond_code = 'if(condOk(CR)) {\n' cond_code += ' ' + br_code + '\n' cond_code += '} else {\n' - cond_code += ' NPC = NPC;\n' + cond_code += ' PCS = PCS;\n' cond_code += '}\n' return cond_code @@ -119,7 +119,7 @@ def GetCtrCondCode(br_code): cond_code += 'if(ctr_ok && cond_ok) {\n' cond_code += ' ' + br_code + '\n' cond_code += '} else {\n' - cond_code += ' NPC = NPC;\n' + cond_code += ' PCS = PCS;\n' cond_code += '}\n' cond_code += 'CTR = ctr;\n' return cond_code diff --git a/src/arch/power/isa/formats/unknown.isa b/src/arch/power/isa/formats/unknown.isa index 06e6ece26..8914cf9a6 100644 --- a/src/arch/power/isa/formats/unknown.isa +++ b/src/arch/power/isa/formats/unknown.isa @@ -76,7 +76,7 @@ output exec {{ { panic("attempt to execute unknown instruction at %#x" "(inst 0x%08x, opcode 0x%x, binary: %s)", - xc->readPC(), machInst, OPCODE, inst2string(machInst)); + xc->pcState().pc(), machInst, OPCODE, inst2string(machInst)); return new UnimplementedOpcodeFault; } }}; diff --git a/src/arch/power/isa/operands.isa b/src/arch/power/isa/operands.isa index fc6c32685..908e6e0e7 100644 --- a/src/arch/power/isa/operands.isa +++ b/src/arch/power/isa/operands.isa @@ -59,8 +59,7 @@ def operands {{ 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 8), # Program counter and next - 'PC': ('PC', 'uw', None, (None, None, 'IsControl'), 9), - 'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 9), + 'PCS': ('PCState', 'uq', None, (None, None, 'IsControl'), 9), # Control registers 'CR': ('IntReg', 'uw', 'INTREG_CR', 'IsInteger', 9), diff --git a/src/arch/power/predecoder.hh b/src/arch/power/predecoder.hh index 1f3ac41cb..b1f2b6e38 100644 --- a/src/arch/power/predecoder.hh +++ b/src/arch/power/predecoder.hh @@ -83,7 +83,7 @@ class Predecoder // Use this to give data to the predecoder. This should be used // when there is control flow. void - moreBytes(Addr pc, Addr fetchPC, MachInst inst) + moreBytes(const PCState &pc, Addr fetchPC, MachInst inst) { emi = inst; } @@ -110,7 +110,7 @@ class Predecoder // This returns a constant reference to the ExtMachInst to avoid a copy const ExtMachInst & - getExtMachInst() + getExtMachInst(PCState &pcState) { return emi; } diff --git a/src/arch/power/process.cc b/src/arch/power/process.cc index 9fb69b9f8..a34a874bc 100644 --- a/src/arch/power/process.cc +++ b/src/arch/power/process.cc @@ -256,9 +256,7 @@ PowerLiveProcess::argsInit(int intSize, int pageSize) //Set the stack pointer register tc->setIntReg(StackPointerReg, stack_min); - Addr prog_entry = objFile->entryPoint(); - tc->setPC(prog_entry); - tc->setNextPC(prog_entry + sizeof(MachInst)); + tc->pcState(objFile->entryPoint()); //Align the "stack_min" to a page boundary. stack_min = roundDown(stack_min, pageSize); diff --git a/src/arch/power/types.hh b/src/arch/power/types.hh index 6a8d1e9d3..d049cdec1 100644 --- a/src/arch/power/types.hh +++ b/src/arch/power/types.hh @@ -31,6 +31,7 @@ #ifndef __ARCH_POWER_TYPES_HH__ #define __ARCH_POWER_TYPES_HH__ +#include "arch/generic/types.hh" #include "base/bitunion.hh" #include "base/hashmap.hh" #include "base/types.hh" @@ -78,6 +79,8 @@ BitUnion32(ExtMachInst) Bitfield<19, 12> fxm; EndBitUnion(ExtMachInst) +typedef GenericISA::SimplePCState<MachInst> PCState; + // typedef uint64_t LargestRead; // // Need to use 64 bits to make sure that read requests get handled properly diff --git a/src/arch/power/utility.cc b/src/arch/power/utility.cc index d48d4870a..399ec1f56 100644 --- a/src/arch/power/utility.cc +++ b/src/arch/power/utility.cc @@ -52,8 +52,7 @@ copyRegs(ThreadContext *src, ThreadContext *dest) copyMiscRegs(src, dest); // Lastly copy PC/NPC - dest->setPC(src->readPC()); - dest->setNextPC(src->readNextPC()); + dest->pcState(src->pcState()); } void diff --git a/src/arch/power/utility.hh b/src/arch/power/utility.hh index c8cd441ba..a47fcdc46 100644 --- a/src/arch/power/utility.hh +++ b/src/arch/power/utility.hh @@ -36,10 +36,19 @@ #define __ARCH_POWER_UTILITY_HH__ #include "base/types.hh" +#include "cpu/static_inst.hh" #include "cpu/thread_context.hh" namespace PowerISA { +inline PCState +buildRetPC(const PCState &curPC, const PCState &callPC) +{ + PCState retPC = callPC; + retPC.advance(); + return retPC; +} + /** * Function to ensure ISA semantics about 0 registers. * @param tc The thread context. @@ -63,6 +72,12 @@ copyMiscRegs(ThreadContext *src, ThreadContext *dest) void skipFunction(ThreadContext *tc); +inline void +advancePC(PCState &pc, const StaticInstPtr inst) +{ + pc.advance(); +} + } // PowerISA namespace #endif // __ARCH_POWER_UTILITY_HH__ |