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Diffstat (limited to 'src/arch/riscv/RiscvInterrupts.py')
| -rw-r--r-- | src/arch/riscv/RiscvInterrupts.py | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/src/arch/riscv/RiscvInterrupts.py b/src/arch/riscv/RiscvInterrupts.py new file mode 100644 index 000000000..57b29b4ca --- /dev/null +++ b/src/arch/riscv/RiscvInterrupts.py @@ -0,0 +1,39 @@ +# Copyright (c) 2008 The Regents of The University of Michigan +# Copyright (c) 2014 Sven Karlsson +# Copyright (c) 2016 RISC-V Foundation +# Copyright (c) 2016 The University of Virginia +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black +# Sven Karlsson +# Alec Roelke + +from m5.SimObject import SimObject + +class RiscvInterrupts(SimObject): + type = 'RiscvInterrupts' + cxx_class = 'RiscvISA::Interrupts' + cxx_header = 'arch/riscv/interrupts.hh' |