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-rw-r--r--src/arch/riscv/RiscvTLB.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/riscv/RiscvTLB.py b/src/arch/riscv/RiscvTLB.py
index bcba00ee0..b24fffb43 100644
--- a/src/arch/riscv/RiscvTLB.py
+++ b/src/arch/riscv/RiscvTLB.py
@@ -32,7 +32,7 @@
from m5.SimObject import SimObject
from m5.params import *
-from BaseTLB import BaseTLB
+from m5.objects.BaseTLB import BaseTLB
class RiscvTLB(BaseTLB):
type = 'RiscvTLB'