diff options
Diffstat (limited to 'src/arch/riscv/faults.hh')
-rw-r--r-- | src/arch/riscv/faults.hh | 77 |
1 files changed, 24 insertions, 53 deletions
diff --git a/src/arch/riscv/faults.hh b/src/arch/riscv/faults.hh index 6d3fdebbe..d9cb44c3d 100644 --- a/src/arch/riscv/faults.hh +++ b/src/arch/riscv/faults.hh @@ -34,8 +34,10 @@ #ifndef __ARCH_RISCV_FAULTS_HH__ #define __ARCH_RISCV_FAULTS_HH__ +#include <map> #include <string> +#include "arch/riscv/isa.hh" #include "arch/riscv/registers.hh" #include "cpu/thread_context.hh" #include "sim/faults.hh" @@ -71,59 +73,12 @@ enum ExceptionCode : MiscReg { AMO_PAGE = 15 }; -/** - * These fields are specified in the RISC-V Instruction Set Manual, Volume II, - * v1.10, accessible at www.riscv.org. in Figure 3.7. The main register that - * uses these fields is the MSTATUS register, which is shadowed by two others - * accessible at lower privilege levels (SSTATUS and USTATUS) that can't see - * the fields for higher privileges. - */ -BitUnion64(STATUS) - Bitfield<63> sd; - Bitfield<35, 34> sxl; - Bitfield<33, 32> uxl; - Bitfield<22> tsr; - Bitfield<21> tw; - Bitfield<20> tvm; - Bitfield<19> mxr; - Bitfield<18> sum; - Bitfield<17> mprv; - Bitfield<16, 15> xs; - Bitfield<14, 13> fs; - Bitfield<12, 11> mpp; - Bitfield<8> spp; - Bitfield<7> mpie; - Bitfield<5> spie; - Bitfield<4> upie; - Bitfield<3> mie; - Bitfield<1> sie; - Bitfield<0> uie; -EndBitUnion(STATUS) - -/** - * These fields are specified in the RISC-V Instruction Set Manual, Volume II, - * v1.10 in Figures 3.11 and 3.12, accessible at www.riscv.org. Both the MIP - * and MIE registers have the same fields, so accesses to either should use - * this bit union. - */ -BitUnion64(INTERRUPT) - Bitfield<11> mei; - Bitfield<9> sei; - Bitfield<8> uei; - Bitfield<7> mti; - Bitfield<5> sti; - Bitfield<4> uti; - Bitfield<3> msi; - Bitfield<1> ssi; - Bitfield<0> usi; -EndBitUnion(INTERRUPT) - class RiscvFault : public FaultBase { protected: const FaultName _name; - bool _interrupt; - const ExceptionCode _code; + const bool _interrupt; + ExceptionCode _code; RiscvFault(FaultName n, bool i, ExceptionCode c) : _name(n), _interrupt(i), _code(c) @@ -254,12 +209,28 @@ class BreakpointFault : public RiscvFault class SyscallFault : public RiscvFault { public: - // TODO: replace ECALL_USER with the appropriate privilege level of the - // caller - SyscallFault() : RiscvFault("System call", false, ECALL_USER) {} + SyscallFault(PrivilegeMode prv) + : RiscvFault("System call", false, ECALL_USER) + { + switch (prv) { + case PRV_U: + _code = ECALL_USER; + break; + case PRV_S: + _code = ECALL_SUPER; + break; + case PRV_M: + _code = ECALL_MACHINE; + break; + default: + panic("Unknown privilege mode %d.", prv); + break; + } + } + void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; }; } // namespace RiscvISA -#endif // __ARCH_RISCV_FAULTS_HH__
\ No newline at end of file +#endif // __ARCH_RISCV_FAULTS_HH__ |