diff options
Diffstat (limited to 'src/arch/riscv/faults.hh')
| -rw-r--r-- | src/arch/riscv/faults.hh | 30 |
1 files changed, 28 insertions, 2 deletions
diff --git a/src/arch/riscv/faults.hh b/src/arch/riscv/faults.hh index 2176f889b..a69b75bc1 100644 --- a/src/arch/riscv/faults.hh +++ b/src/arch/riscv/faults.hh @@ -34,7 +34,6 @@ #ifndef __ARCH_RISCV_FAULTS_HH__ #define __ARCH_RISCV_FAULTS_HH__ -#include <map> #include <string> #include "arch/riscv/isa.hh" @@ -53,6 +52,15 @@ enum FloatException : MiscReg { FloatInvalid = 0x10 }; +/* + * In RISC-V, exception and interrupt codes share some values. They can be + * differentiated by an 'Interrupt' flag that is enabled for interrupt faults + * but not exceptions. The full fault cause can be computed by placing the + * exception (or interrupt) code in the least significant bits of the CAUSE + * CSR and then setting the highest bit of CAUSE with the 'Interrupt' flag. + * For more details on exception causes, see Chapter 3.1.20 of the RISC-V + * privileged specification v 1.10. Codes are enumerated in Table 3.6. + */ enum ExceptionCode : MiscReg { INST_ADDR_MISALIGNED = 0, INST_ACCESS = 1, @@ -70,7 +78,18 @@ enum ExceptionCode : MiscReg { INST_PAGE = 12, LOAD_PAGE = 13, STORE_PAGE = 15, - AMO_PAGE = 15 + AMO_PAGE = 15, + + INT_SOFTWARE_USER = 0, + INT_SOFTWARE_SUPER = 1, + INT_SOFTWARE_MACHINE = 3, + INT_TIMER_USER = 4, + INT_TIMER_SUPER = 5, + INT_TIMER_MACHINE = 7, + INT_EXT_USER = 8, + INT_EXT_SUPER = 9, + INT_EXT_MACHINE = 11, + NumInterruptTypes }; class RiscvFault : public FaultBase @@ -106,6 +125,13 @@ class Reset : public FaultBase StaticInst::nullStaticInstPtr) override; }; +class InterruptFault : public RiscvFault +{ + public: + InterruptFault(ExceptionCode c) : RiscvFault("interrupt", true, c) {} + InterruptFault(int c) : InterruptFault(static_cast<ExceptionCode>(c)) {} +}; + class InstFault : public RiscvFault { protected: |