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Diffstat (limited to 'src/arch/riscv/insts/amo.cc')
-rw-r--r--src/arch/riscv/insts/amo.cc38
1 files changed, 30 insertions, 8 deletions
diff --git a/src/arch/riscv/insts/amo.cc b/src/arch/riscv/insts/amo.cc
index d12064720..ce20e6064 100644
--- a/src/arch/riscv/insts/amo.cc
+++ b/src/arch/riscv/insts/amo.cc
@@ -34,6 +34,7 @@
#include <sstream>
#include <string>
+#include "arch/riscv/insts/bitfields.hh"
#include "arch/riscv/utility.hh"
#include "cpu/exec_context.hh"
#include "cpu/static_inst.hh"
@@ -63,8 +64,15 @@ string LoadReserved::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
stringstream ss;
- ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", ("
- << registerName(_srcRegIdx[0]) << ')';
+ ss << mnemonic;
+ if (AQ || RL)
+ ss << '_';
+ if (AQ)
+ ss << "aq";
+ if (RL)
+ ss << "rl";
+ ss << ' ' << registerName(RegId(IntRegClass, RD)) << ", ("
+ << registerName(RegId(IntRegClass, RS1)) << ')';
return ss.str();
}
@@ -82,9 +90,16 @@ string StoreCond::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
stringstream ss;
- ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", "
- << registerName(_srcRegIdx[1]) << ", ("
- << registerName(_srcRegIdx[0]) << ')';
+ ss << mnemonic;
+ if (AQ || RL)
+ ss << '_';
+ if (AQ)
+ ss << "aq";
+ if (RL)
+ ss << "rl";
+ ss << ' ' << registerName(RegId(IntRegClass, RD)) << ", "
+ << registerName(RegId(IntRegClass, RS2)) << ", ("
+ << registerName(RegId(IntRegClass, RS1)) << ')';
return ss.str();
}
@@ -103,9 +118,16 @@ string AtomicMemOp::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
stringstream ss;
- ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", "
- << registerName(_srcRegIdx[1]) << ", ("
- << registerName(_srcRegIdx[0]) << ')';
+ ss << mnemonic;
+ if (AQ || RL)
+ ss << '_';
+ if (AQ)
+ ss << "aq";
+ if (RL)
+ ss << "rl";
+ ss << ' ' << registerName(RegId(IntRegClass, RD)) << ", "
+ << registerName(RegId(IntRegClass, RS2)) << ", ("
+ << registerName(RegId(IntRegClass, RS1)) << ')';
return ss.str();
}