diff options
Diffstat (limited to 'src/arch/riscv/insts')
| -rw-r--r-- | src/arch/riscv/insts/bitfields.hh | 1 | ||||
| -rw-r--r-- | src/arch/riscv/insts/unknown.hh | 74 |
2 files changed, 75 insertions, 0 deletions
diff --git a/src/arch/riscv/insts/bitfields.hh b/src/arch/riscv/insts/bitfields.hh index 45744e081..d6648227e 100644 --- a/src/arch/riscv/insts/bitfields.hh +++ b/src/arch/riscv/insts/bitfields.hh @@ -5,5 +5,6 @@ #define CSRIMM bits(machInst, 19, 15) #define FUNCT12 bits(machInst, 31, 20) +#define OPCODE bits(machInst, 6, 0) #endif // __ARCH_RISCV_BITFIELDS_HH__
\ No newline at end of file diff --git a/src/arch/riscv/insts/unknown.hh b/src/arch/riscv/insts/unknown.hh new file mode 100644 index 000000000..049f879de --- /dev/null +++ b/src/arch/riscv/insts/unknown.hh @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2015 RISC-V Foundation + * Copyright (c) 2017 The University of Virginia + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Alec Roelke + */ + +#ifndef __ARCH_RISCV_UNKNOWN_INST_HH__ +#define __ARCH_RISCV_UNKNOWN_INST_HH__ + +#include <memory> +#include <string> + +#include "arch/riscv/faults.hh" +#include "arch/riscv/insts/bitfields.hh" +#include "arch/riscv/insts/static_inst.hh" +#include "cpu/exec_context.hh" +#include "cpu/static_inst.hh" + +namespace RiscvISA +{ + +/** + * Static instruction class for unknown (illegal) instructions. + * These cause simulator termination if they are executed in a + * non-speculative mode. This is a leaf class. + */ +class Unknown : public RiscvStaticInst +{ + public: + Unknown(MachInst _machInst) + : RiscvStaticInst("unknown", _machInst, No_OpClass) + {} + + Fault + execute(ExecContext *, Trace::InstRecord *) const override + { + return std::make_shared<UnknownInstFault>(); + } + + std::string + generateDisassembly(Addr pc, const SymbolTable *symtab) const override + { + return csprintf("unknown opcode %#02x", OPCODE); + } +}; + +} + +#endif // __ARCH_RISCV_UNKNOWN_INST_HH__
\ No newline at end of file |