diff options
Diffstat (limited to 'src/arch/riscv/interrupts.hh')
-rw-r--r-- | src/arch/riscv/interrupts.hh | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/src/arch/riscv/interrupts.hh b/src/arch/riscv/interrupts.hh index cfb9a5b7e..60a5b5bc5 100644 --- a/src/arch/riscv/interrupts.hh +++ b/src/arch/riscv/interrupts.hh @@ -32,6 +32,7 @@ #define __ARCH_RISCV_INTERRUPT_HH__ #include "base/logging.hh" +#include "cpu/thread_context.hh" #include "params/RiscvInterrupts.hh" #include "sim/sim_object.hh" @@ -78,13 +79,23 @@ class Interrupts : public SimObject void clearAll() { - panic("Interrupts::clearAll not implemented.\n"); + warn_once("Interrupts::clearAll not implemented.\n"); } bool checkInterrupts(ThreadContext *tc) const { - panic("Interrupts::checkInterrupts not implemented.\n"); + warn_once("Interrupts::checkInterrupts just rudimentary implemented"); + /** + * read the machine interrupt register in order to check if interrupts + * are pending + * should be sufficient for now, as interrupts + * are not implemented at all + */ + if (tc->readMiscReg(MISCREG_IP)) + return true; + + return false; } Fault |