diff options
Diffstat (limited to 'src/arch/riscv/isa.cc')
| -rw-r--r-- | src/arch/riscv/isa.cc | 31 |
1 files changed, 23 insertions, 8 deletions
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc index cc86752ab..0fa730533 100644 --- a/src/arch/riscv/isa.cc +++ b/src/arch/riscv/isa.cc @@ -34,6 +34,7 @@ #include <set> #include <sstream> +#include "arch/riscv/interrupts.hh" #include "arch/riscv/registers.hh" #include "base/bitfield.hh" #include "cpu/base.hh" @@ -142,11 +143,17 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) return 0; } case MISCREG_IP: - return tc->getCpuPtr()->getInterruptController(tc->threadId()) - ->readIP(); + { + auto ic = dynamic_cast<RiscvISA::Interrupts *>( + tc->getCpuPtr()->getInterruptController(tc->threadId())); + return ic->readIP(); + } case MISCREG_IE: - return tc->getCpuPtr()->getInterruptController(tc->threadId()) - ->readIE(); + { + auto ic = dynamic_cast<RiscvISA::Interrupts *>( + tc->getCpuPtr()->getInterruptController(tc->threadId())); + return ic->readIE(); + } default: // Try reading HPM counters // As a placeholder, all HPM counters are just cycle counters @@ -185,11 +192,19 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) } else { switch (misc_reg) { case MISCREG_IP: - return tc->getCpuPtr()->getInterruptController(tc->threadId()) - ->setIP(val); + { + auto ic = dynamic_cast<RiscvISA::Interrupts *>( + tc->getCpuPtr()->getInterruptController(tc->threadId())); + ic->setIP(val); + } + break; case MISCREG_IE: - return tc->getCpuPtr()->getInterruptController(tc->threadId()) - ->setIE(val); + { + auto ic = dynamic_cast<RiscvISA::Interrupts *>( + tc->getCpuPtr()->getInterruptController(tc->threadId())); + ic->setIE(val); + } + break; default: setMiscRegNoEffect(misc_reg, val); } |