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-rw-r--r--src/arch/riscv/isa.hh7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index d2f38b158..3f2412303 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -44,6 +44,7 @@
#include "arch/riscv/registers.hh"
#include "arch/riscv/types.hh"
#include "base/misc.hh"
+#include "cpu/reg_class.hh"
#include "sim/sim_object.hh"
struct RiscvISAParams;
@@ -78,6 +79,12 @@ class ISA : public SimObject
void
setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
+ RegId
+ flattenRegId(const RegId &regId) const
+ {
+ return regId;
+ }
+
int
flattenIntIndex(int reg) const
{