summaryrefslogtreecommitdiff
path: root/src/arch/riscv/isa.hh
diff options
context:
space:
mode:
Diffstat (limited to 'src/arch/riscv/isa.hh')
-rw-r--r--src/arch/riscv/isa.hh4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index f96b07275..2602f6dde 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -76,8 +76,8 @@ class ISA : public SimObject
MiscReg readMiscRegNoEffect(int misc_reg) const;
MiscReg readMiscReg(int misc_reg, ThreadContext *tc);
- void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
- void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
+ void setMiscRegNoEffect(int misc_reg, MiscReg val);
+ void setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc);
RegId flattenRegId(const RegId &regId) const { return regId; }
int flattenIntIndex(int reg) const { return reg; }