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-rw-r--r--src/arch/riscv/isa/decoder.isa10
1 files changed, 8 insertions, 2 deletions
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 4f4ef7636..0e5567ac3 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -42,7 +42,8 @@ decode QUADRANT default Unknown::unknown() {
CIMM8<7:6> << 4 |
CIMM8<5:2> << 6;
}}, {{
- assert(imm != 0);
+ if (machInst == 0)
+ fault = make_shared<IllegalInstFault>("zero instruction");
Rp2 = sp + imm;
}});
format CompressedLoad {
@@ -103,7 +104,12 @@ decode QUADRANT default Unknown::unknown() {
if (CIMM1 > 0)
imm |= ~((uint64_t)0x1F);
}}, {{
- assert((RC1 == 0) == (imm == 0));
+ if ((RC1 == 0) != (imm == 0)) {
+ if (RC1 == 0) {
+ fault = make_shared<IllegalInstFault>("source reg x0");
+ } else // imm == 0
+ fault = make_shared<IllegalInstFault>("immediate = 0");
+ }
Rc1_sd = Rc1_sd + imm;
}});
0x1: c_addiw({{