diff options
Diffstat (limited to 'src/arch/riscv/isa/formats/fp.isa')
| -rw-r--r-- | src/arch/riscv/isa/formats/fp.isa | 12 |
1 files changed, 2 insertions, 10 deletions
diff --git a/src/arch/riscv/isa/formats/fp.isa b/src/arch/riscv/isa/formats/fp.isa index 97a5a2a50..1f60b9b70 100644 --- a/src/arch/riscv/isa/formats/fp.isa +++ b/src/arch/riscv/isa/formats/fp.isa @@ -1,7 +1,7 @@ // -*- mode:c++ -*- // Copyright (c) 2015 Riscv Developers -// Copyright (c) 2016 The University of Virginia +// Copyright (c) 2016-2017 The University of Virginia // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -120,15 +120,7 @@ def template FloatExecute {{ }}; def format FPROp(code, *opt_flags) {{ - iop = InstObjParams(name, Name, 'ROp', code, opt_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecode.subst(iop) - exec_output = FloatExecute.subst(iop) -}}; - -def format FPR4Op(code, *opt_flags) {{ - iop = InstObjParams(name, Name, 'ROp', code, opt_flags) + iop = InstObjParams(name, Name, 'RegOp', code, opt_flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) decode_block = BasicDecode.subst(iop) |