diff options
Diffstat (limited to 'src/arch/riscv/isa/formats/mem.isa')
| -rw-r--r-- | src/arch/riscv/isa/formats/mem.isa | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/riscv/isa/formats/mem.isa b/src/arch/riscv/isa/formats/mem.isa index 2a00850a2..4ae8eb41a 100644 --- a/src/arch/riscv/isa/formats/mem.isa +++ b/src/arch/riscv/isa/formats/mem.isa @@ -87,8 +87,8 @@ output decoder {{ Load::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; - ss << mnemonic << ' ' << regName(_destRegIdx[0]) << ", " << ldisp << - '(' << regName(_srcRegIdx[0]) << ')'; + ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " << + ldisp << '(' << registerName(_srcRegIdx[0]) << ')'; return ss.str(); } @@ -96,8 +96,8 @@ output decoder {{ Store::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; - ss << mnemonic << ' ' << regName(_srcRegIdx[1]) << ", " << sdisp << - '(' << regName(_srcRegIdx[0]) << ')'; + ss << mnemonic << ' ' << registerName(_srcRegIdx[1]) << ", " << + sdisp << '(' << registerName(_srcRegIdx[0]) << ')'; return ss.str(); } }}; |