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Diffstat (limited to 'src/arch/riscv/isa/formats/mem.isa')
-rw-r--r--src/arch/riscv/isa/formats/mem.isa20
1 files changed, 6 insertions, 14 deletions
diff --git a/src/arch/riscv/isa/formats/mem.isa b/src/arch/riscv/isa/formats/mem.isa
index 2cb2f18b4..11b6c4238 100644
--- a/src/arch/riscv/isa/formats/mem.isa
+++ b/src/arch/riscv/isa/formats/mem.isa
@@ -254,25 +254,17 @@ def template StoreCompleteAcc {{
}
}};
-def format Load(memacc_code, ea_code={{EA = Rs1 + offset;}}, mem_flags=[],
- inst_flags=[]) {{
- offset_code = """
- offset = IMM12;
- if (IMMSIGN > 0)
- offset |= ~((uint64_t)0xFFF);
- """
+def format Load(memacc_code, ea_code = {{EA = Rs1 + offset;}},
+ offset_code={{offset = sext<12>(IMM12);}},
+ mem_flags=[], inst_flags=[]) {{
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, offset_code, ea_code, memacc_code, mem_flags,
inst_flags, 'Load', exec_template_base='Load')
}};
-def format Store(memacc_code, ea_code={{EA = Rs1 + offset;}}, mem_flags=[],
- inst_flags=[]) {{
- offset_code = """
- offset = IMM5 | (IMM7 << 5);
- if (IMMSIGN > 0)
- offset |= ~((uint64_t)0xFFF);
- """
+def format Store(memacc_code, ea_code={{EA = Rs1 + offset;}},
+ offset_code={{offset = sext<12>(IMM5 | (IMM7 << 5));}},
+ mem_flags=[], inst_flags=[]) {{
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, offset_code, ea_code, memacc_code, mem_flags,
inst_flags, 'Store', exec_template_base='Store')