diff options
Diffstat (limited to 'src/arch/riscv/isa/formats/mem.isa')
-rw-r--r-- | src/arch/riscv/isa/formats/mem.isa | 81 |
1 files changed, 81 insertions, 0 deletions
diff --git a/src/arch/riscv/isa/formats/mem.isa b/src/arch/riscv/isa/formats/mem.isa index 2a00850a2..bea649c04 100644 --- a/src/arch/riscv/isa/formats/mem.isa +++ b/src/arch/riscv/isa/formats/mem.isa @@ -186,6 +186,10 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, # select templates + # The InitiateAcc template is the same for StoreCond templates as the + # corresponding Store template.. + StoreCondInitiateAcc = StoreInitiateAcc + fullExecTemplate = eval(exec_template_base + 'Execute') initiateAccTemplate = eval(exec_template_base + 'InitiateAcc') completeAccTemplate = eval(exec_template_base + 'CompleteAcc') @@ -340,6 +344,61 @@ def template StoreCompleteAcc {{ } }}; +def template StoreCondExecute {{ + Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Trace::InstRecord *traceData) const + { + Addr EA; + Fault fault = NoFault; + uint64_t result; + + %(op_decl)s; + %(op_rd)s; + %(ea_code)s; + + if (fault == NoFault) { + %(memacc_code)s; + } + + if (fault == NoFault) { + fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, + &result); + } + + if (fault == NoFault) { + %(postacc_code)s; + } + + if (fault == NoFault) { + %(op_wb)s; + } + + return fault; + } +}}; + +def template StoreCondCompleteAcc {{ + Fault %(class_name)s::completeAcc(Packet *pkt, CPU_EXEC_CONTEXT *xc, + Trace::InstRecord *traceData) const + { + Fault fault = NoFault; + + %(op_dest_decl)s; + + uint64_t result = pkt->req->getExtraData(); + + if (fault == NoFault) { + %(postacc_code)s; + } + + if (fault == NoFault) { + %(op_wb)s; + } + + return fault; + } +}}; + def format Load(memacc_code, ea_code = {{EA = Rs1 + ldisp;}}, mem_flags=[], inst_flags=[]) {{ (header_output, decoder_output, decode_block, exec_output) = \ @@ -353,3 +412,25 @@ def format Store(memacc_code, ea_code={{EA = Rs1 + sdisp;}}, mem_flags=[], LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 'Store', exec_template_base='Store') }}; + +def format StoreCond(memacc_code, postacc_code, ea_code={{EA = Rs1;}}, + mem_flags=[], inst_flags=[], aq=0, rl=0) {{ + if aq: + mem_flags = makeList(mem_flags) + ["ACQUIRE"] + if rl: + mem_flags = makeList(mem_flags) + ["RELEASE"] + (header_output, decoder_output, decode_block, exec_output) = LoadStoreBase( + name, Name, ea_code, memacc_code, mem_flags, inst_flags, 'Store', + postacc_code, exec_template_base='StoreCond') +}}; + +def format LoadReserved(memacc_code, ea_code={{EA = Rs1;}}, mem_flags=[], + inst_flags=[], aq=0, rl=0) {{ + if aq: + mem_flags = makeList(mem_flags) + ["ACQUIRE"] + if rl: + mem_flags = makeList(mem_flags) + ["RELEASE"] + (header_output, decoder_output, decode_block, exec_output) = LoadStoreBase( + name, Name, ea_code, memacc_code, mem_flags, inst_flags, 'Load', + exec_template_base='Load') +}}; |