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-rw-r--r--src/arch/riscv/isa/formats/amo.isa18
-rw-r--r--src/arch/riscv/isa/formats/basic.isa4
-rw-r--r--src/arch/riscv/isa/formats/fp.isa2
-rw-r--r--src/arch/riscv/isa/formats/mem.isa23
-rw-r--r--src/arch/riscv/isa/formats/standard.isa12
-rw-r--r--src/arch/riscv/isa/formats/unknown.isa2
6 files changed, 30 insertions, 31 deletions
diff --git a/src/arch/riscv/isa/formats/amo.isa b/src/arch/riscv/isa/formats/amo.isa
index 24e13c984..983c1f4cc 100644
--- a/src/arch/riscv/isa/formats/amo.isa
+++ b/src/arch/riscv/isa/formats/amo.isa
@@ -223,7 +223,7 @@ def template AtomicMemOpStoreConstructor {{
}};
def template StoreCondExecute {{
- Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
+ Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
@@ -259,7 +259,7 @@ def template StoreCondExecute {{
}};
def template AtomicMemOpLoadExecute {{
- Fault %(class_name)s::%(class_name)sLoad::execute(CPU_EXEC_CONTEXT *xc,
+ Fault %(class_name)s::%(class_name)sLoad::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
@@ -286,7 +286,7 @@ def template AtomicMemOpLoadExecute {{
}};
def template AtomicMemOpStoreExecute {{
- Fault %(class_name)s::%(class_name)sStore::execute(CPU_EXEC_CONTEXT *xc,
+ Fault %(class_name)s::%(class_name)sStore::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
@@ -315,7 +315,7 @@ def template AtomicMemOpStoreExecute {{
def template AtomicMemOpEACompExecute {{
Fault
- %(class_name)s::%(class_name)s%(op_name)s::eaComp(CPU_EXEC_CONTEXT *xc,
+ %(class_name)s::%(class_name)s%(op_name)s::eaComp(ExecContext *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
@@ -335,7 +335,7 @@ def template AtomicMemOpEACompExecute {{
}};
def template AtomicMemOpLoadInitiateAcc {{
- Fault %(class_name)s::%(class_name)sLoad::initiateAcc(CPU_EXEC_CONTEXT *xc,
+ Fault %(class_name)s::%(class_name)sLoad::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
@@ -355,7 +355,7 @@ def template AtomicMemOpLoadInitiateAcc {{
def template AtomicMemOpStoreInitiateAcc {{
Fault %(class_name)s::%(class_name)sStore::initiateAcc(
- CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -382,7 +382,7 @@ def template AtomicMemOpStoreInitiateAcc {{
}};
def template StoreCondCompleteAcc {{
- Fault %(class_name)s::completeAcc(Packet *pkt, CPU_EXEC_CONTEXT *xc,
+ Fault %(class_name)s::completeAcc(Packet *pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -407,7 +407,7 @@ def template StoreCondCompleteAcc {{
def template AtomicMemOpLoadCompleteAcc {{
Fault %(class_name)s::%(class_name)sLoad::completeAcc(PacketPtr pkt,
- CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -430,7 +430,7 @@ def template AtomicMemOpLoadCompleteAcc {{
def template AtomicMemOpStoreCompleteAcc {{
Fault %(class_name)s::%(class_name)sStore::completeAcc(PacketPtr pkt,
- CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, Trace::InstRecord *traceData) const
{
return NoFault;
}
diff --git a/src/arch/riscv/isa/formats/basic.isa b/src/arch/riscv/isa/formats/basic.isa
index 4126fcdd4..2d27fd8b5 100644
--- a/src/arch/riscv/isa/formats/basic.isa
+++ b/src/arch/riscv/isa/formats/basic.isa
@@ -32,7 +32,7 @@
// Declarations for execute() methods.
def template BasicExecDeclare {{
- Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
}};
// Basic instruction class declaration template.
@@ -63,7 +63,7 @@ def template BasicConstructor {{
// Basic instruction class execute method template.
def template BasicExecute {{
Fault
- %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
+ %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
diff --git a/src/arch/riscv/isa/formats/fp.isa b/src/arch/riscv/isa/formats/fp.isa
index 3de0bb2ff..1f08ca512 100644
--- a/src/arch/riscv/isa/formats/fp.isa
+++ b/src/arch/riscv/isa/formats/fp.isa
@@ -34,7 +34,7 @@
// Floating point operation instructions
//
def template FloatExecute {{
- Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
+ Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
diff --git a/src/arch/riscv/isa/formats/mem.isa b/src/arch/riscv/isa/formats/mem.isa
index 9b6bc9eb5..5f469dc8d 100644
--- a/src/arch/riscv/isa/formats/mem.isa
+++ b/src/arch/riscv/isa/formats/mem.isa
@@ -121,18 +121,18 @@ def template LoadStoreDeclare {{
def template EACompDeclare {{
Fault
- eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const;
+ eaComp(ExecContext *, Trace::InstRecord *) const;
}};
def template InitiateAccDeclare {{
Fault
- initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
+ initiateAcc(ExecContext *, Trace::InstRecord *) const;
}};
def template CompleteAccDeclare {{
Fault
- completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
+ completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
}};
def template LoadStoreConstructor {{
@@ -146,8 +146,7 @@ def template LoadStoreConstructor {{
def template EACompExecute {{
Fault
- %(class_name)s::eaComp(CPU_EXEC_CONTEXT *xc,
- Trace::InstRecord *traceData) const
+ %(class_name)s::eaComp(ExecContext *xc, Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -201,8 +200,8 @@ def LoadStoreBase(name, Name, offset_code, ea_code, memacc_code, mem_flags,
def template LoadExecute {{
Fault
- %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
- Trace::InstRecord *traceData) const
+ %(class_name)s::execute(
+ ExecContext *xc, Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -226,7 +225,7 @@ def template LoadExecute {{
def template LoadInitiateAcc {{
Fault
- %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc,
+ %(class_name)s::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
@@ -246,7 +245,7 @@ def template LoadInitiateAcc {{
def template LoadCompleteAcc {{
Fault
- %(class_name)s::completeAcc(PacketPtr pkt, CPU_EXEC_CONTEXT *xc,
+ %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -270,7 +269,7 @@ def template LoadCompleteAcc {{
def template StoreExecute {{
Fault
- %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
+ %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
@@ -303,7 +302,7 @@ def template StoreExecute {{
def template StoreInitiateAcc {{
Fault
- %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc,
+ %(class_name)s::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
@@ -332,7 +331,7 @@ def template StoreInitiateAcc {{
def template StoreCompleteAcc {{
Fault
- %(class_name)s::completeAcc(PacketPtr pkt, CPU_EXEC_CONTEXT *xc,
+ %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
{
return NoFault;
diff --git a/src/arch/riscv/isa/formats/standard.isa b/src/arch/riscv/isa/formats/standard.isa
index 4ef241b2c..70d6ada33 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -201,8 +201,8 @@ def template ImmConstructor {{
def template ImmExecute {{
Fault
- %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
- Trace::InstRecord *traceData) const
+ %(class_name)s::execute(
+ ExecContext *xc, Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -254,7 +254,7 @@ def template BranchDeclare {{
def template BranchExecute {{
Fault
- %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
+ %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -313,8 +313,8 @@ def template JumpDeclare {{
def template JumpExecute {{
Fault
- %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
- Trace::InstRecord *traceData) const
+ %(class_name)s::execute(
+ ExecContext *xc, Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -446,4 +446,4 @@ def format CSROp(code, *opt_flags) {{
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = BasicExecute.subst(iop)
-}}; \ No newline at end of file
+}};
diff --git a/src/arch/riscv/isa/formats/unknown.isa b/src/arch/riscv/isa/formats/unknown.isa
index 7a3023a14..aaab21137 100644
--- a/src/arch/riscv/isa/formats/unknown.isa
+++ b/src/arch/riscv/isa/formats/unknown.isa
@@ -68,7 +68,7 @@ output decoder {{
output exec {{
Fault
- Unknown::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
+ Unknown::execute(ExecContext *xc, Trace::InstRecord *traceData) const
{
Fault fault = std::make_shared<UnknownInstFault>();
return fault;
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-05 04:32:20 +0000