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Diffstat (limited to 'src/arch/riscv/isa/includes.isa')
-rw-r--r-- | src/arch/riscv/isa/includes.isa | 90 |
1 files changed, 90 insertions, 0 deletions
diff --git a/src/arch/riscv/isa/includes.isa b/src/arch/riscv/isa/includes.isa new file mode 100644 index 000000000..197133d25 --- /dev/null +++ b/src/arch/riscv/isa/includes.isa @@ -0,0 +1,90 @@ +// -*- mode:c++ -*- + +// Copyright (c) 2015 RISC-V Foundation +// Copyright (c) 2016 The University of Virginia +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer; +// redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution; +// neither the name of the copyright holders nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Authors: Maxwell Walter +// Alec Roelke + +//////////////////////////////////////////////////////////////////// +// +// Output include file directives. +// + +output header {{ +#include <iomanip> +#include <sstream> +#include <string> +#include <tuple> +#include <vector> + +#include "cpu/static_inst.hh" +#include "mem/packet.hh" +#include "mem/request.hh" + +}}; + +output decoder {{ +#include <cfenv> +#include <cmath> +#include <limits> +#include <string> + +#include "arch/riscv/decoder.hh" +#include "arch/riscv/faults.hh" +#include "arch/riscv/tlb.hh" +#include "base/cprintf.hh" +#include "base/loader/symtab.hh" +#include "cpu/thread_context.hh" +#include "mem/packet.hh" +#include "mem/request.hh" +#include "sim/full_system.hh" + +using namespace RiscvISA; +}}; + +output exec {{ +#include <cmath> +#include <string> + +#include "arch/generic/memhelpers.hh" +#include "arch/riscv/faults.hh" +#include "arch/riscv/registers.hh" +#include "base/condcodes.hh" +#include "cpu/base.hh" +#include "cpu/exetrace.hh" +#include "mem/packet.hh" +#include "mem/packet_access.hh" +#include "mem/request.hh" +#include "sim/eventq.hh" +#include "sim/full_system.hh" +#include "sim/sim_events.hh" +#include "sim/sim_exit.hh" +#include "sim/system.hh" + +using namespace RiscvISA; +}}; |