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Diffstat (limited to 'src/arch/riscv/isa/operands.isa')
| -rw-r--r-- | src/arch/riscv/isa/operands.isa | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/riscv/isa/operands.isa b/src/arch/riscv/isa/operands.isa index 5e79717e7..7a8385d0c 100644 --- a/src/arch/riscv/isa/operands.isa +++ b/src/arch/riscv/isa/operands.isa @@ -48,6 +48,7 @@ def operands {{ 'Rd': ('IntReg', 'ud', 'RD', 'IsInteger', 1), 'Rs1': ('IntReg', 'ud', 'RS1', 'IsInteger', 2), 'Rs2': ('IntReg', 'ud', 'RS2', 'IsInteger', 3), + 'Rt': ('IntReg', 'ud', 'AMOTempReg', 'IsInteger', 4), 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 1), 'Fd_bits': ('FloatReg', 'ud', 'FD', 'IsFloating', 1), |