diff options
Diffstat (limited to 'src/arch/riscv/isa/operands.isa')
| -rw-r--r-- | src/arch/riscv/isa/operands.isa | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/arch/riscv/isa/operands.isa b/src/arch/riscv/isa/operands.isa index d6bdda399..5e79717e7 100644 --- a/src/arch/riscv/isa/operands.isa +++ b/src/arch/riscv/isa/operands.isa @@ -39,6 +39,8 @@ def operand_types {{ 'uw' : 'uint32_t', 'sd' : 'int64_t', 'ud' : 'uint64_t', + 'sf' : 'float', + 'df' : 'double' }}; def operands {{ @@ -47,6 +49,15 @@ def operands {{ 'Rs1': ('IntReg', 'ud', 'RS1', 'IsInteger', 2), 'Rs2': ('IntReg', 'ud', 'RS2', 'IsInteger', 3), + 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 1), + 'Fd_bits': ('FloatReg', 'ud', 'FD', 'IsFloating', 1), + 'Fs1': ('FloatReg', 'df', 'FS1', 'IsFloating', 2), + 'Fs1_bits': ('FloatReg', 'ud', 'FS1', 'IsFloating', 2), + 'Fs2': ('FloatReg', 'df', 'FS2', 'IsFloating', 3), + 'Fs2_bits': ('FloatReg', 'ud', 'FS2', 'IsFloating', 3), + 'Fs3': ('FloatReg', 'df', 'FS3', 'IsFloating', 4), + 'Fs3_bits': ('FloatReg', 'ud', 'FS3', 'IsFloating', 4), + #Memory Operand 'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 5), |