diff options
Diffstat (limited to 'src/arch/riscv/isa')
| -rw-r--r-- | src/arch/riscv/isa/formats/compressed.isa | 29 | ||||
| -rw-r--r-- | src/arch/riscv/isa/includes.isa | 1 |
2 files changed, 1 insertions, 29 deletions
diff --git a/src/arch/riscv/isa/formats/compressed.isa b/src/arch/riscv/isa/formats/compressed.isa index 683795d89..3c47a906f 100644 --- a/src/arch/riscv/isa/formats/compressed.isa +++ b/src/arch/riscv/isa/formats/compressed.isa @@ -28,35 +28,6 @@ // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // // Authors: Alec Roelke - -output header {{ - /** - * Base class for compressed operations that work only on registers - */ - class CompRegOp : public RiscvStaticInst - { - protected: - /// Constructor - CompRegOp(const char *mnem, MachInst _machInst, OpClass __opClass) - : RiscvStaticInst(mnem, _machInst, __opClass) - {} - - std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; -}}; - -output decoder {{ - std::string - CompRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - std::stringstream ss; - ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " << - registerName(_srcRegIdx[0]); - return ss.str(); - } -}}; - def format CROp(code, *opt_flags) {{ iop = InstObjParams(name, Name, 'CompRegOp', code, opt_flags) header_output = BasicDeclare.subst(iop) diff --git a/src/arch/riscv/isa/includes.isa b/src/arch/riscv/isa/includes.isa index f4662dacf..9f3d99fb5 100644 --- a/src/arch/riscv/isa/includes.isa +++ b/src/arch/riscv/isa/includes.isa @@ -43,6 +43,7 @@ output header {{ #include <vector> #include "arch/riscv/insts/amo.hh" +#include "arch/riscv/insts/compressed.hh" #include "arch/riscv/insts/mem.hh" #include "arch/riscv/insts/standard.hh" #include "arch/riscv/insts/static_inst.hh" |