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Diffstat (limited to 'src/arch/riscv/isa')
-rw-r--r--src/arch/riscv/isa/decoder.isa73
-rw-r--r--src/arch/riscv/isa/formats/fp.isa9
-rw-r--r--src/arch/riscv/isa/formats/standard.isa4
3 files changed, 55 insertions, 31 deletions
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index b4bf3854b..a0e3ad19d 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -43,7 +43,8 @@ decode QUADRANT default Unknown::unknown() {
CIMM8<5:2> << 6;
}}, {{
if (machInst == 0)
- fault = make_shared<IllegalInstFault>("zero instruction");
+ fault = make_shared<IllegalInstFault>("zero instruction",
+ machInst);
Rp2 = sp + imm;
}}, uint64_t);
format CompressedLoad {
@@ -106,9 +107,11 @@ decode QUADRANT default Unknown::unknown() {
}}, {{
if ((RC1 == 0) != (imm == 0)) {
if (RC1 == 0) {
- fault = make_shared<IllegalInstFault>("source reg x0");
+ fault = make_shared<IllegalInstFault>("source reg x0",
+ machInst);
} else // imm == 0
- fault = make_shared<IllegalInstFault>("immediate = 0");
+ fault = make_shared<IllegalInstFault>("immediate = 0",
+ machInst);
}
Rc1_sd = Rc1_sd + imm;
}});
@@ -118,7 +121,8 @@ decode QUADRANT default Unknown::unknown() {
imm |= ~((uint64_t)0x1F);
}}, {{
if (RC1 == 0) {
- fault = make_shared<IllegalInstFault>("source reg x0");
+ fault = make_shared<IllegalInstFault>("source reg x0",
+ machInst);
}
Rc1_sd = (int32_t)Rc1_sd + imm;
}});
@@ -128,7 +132,8 @@ decode QUADRANT default Unknown::unknown() {
imm |= ~((uint64_t)0x1F);
}}, {{
if (RC1 == 0) {
- fault = make_shared<IllegalInstFault>("source reg x0");
+ fault = make_shared<IllegalInstFault>("source reg x0",
+ machInst);
}
Rc1_sd = imm;
}});
@@ -142,7 +147,8 @@ decode QUADRANT default Unknown::unknown() {
imm |= ~((int64_t)0x1FF);
}}, {{
if (imm == 0) {
- fault = make_shared<IllegalInstFault>("immediate = 0");
+ fault = make_shared<IllegalInstFault>("immediate = 0",
+ machInst);
}
sp_sd = sp_sd + imm;
}});
@@ -152,10 +158,12 @@ decode QUADRANT default Unknown::unknown() {
imm |= ~((uint64_t)0x1FFFF);
}}, {{
if (RC1 == 0 || RC1 == 2) {
- fault = make_shared<IllegalInstFault>("source reg x0");
+ fault = make_shared<IllegalInstFault>("source reg x0",
+ machInst);
}
if (imm == 0) {
- fault = make_shared<IllegalInstFault>("immediate = 0");
+ fault = make_shared<IllegalInstFault>("immediate = 0",
+ machInst);
}
Rc1_sd = imm;
}});
@@ -167,7 +175,8 @@ decode QUADRANT default Unknown::unknown() {
imm = CIMM5 | (CIMM1 << 5);
}}, {{
if (imm == 0) {
- fault = make_shared<IllegalInstFault>("immediate = 0");
+ fault = make_shared<IllegalInstFault>("immediate = 0",
+ machInst);
}
Rp1 = Rp1 >> imm;
}}, uint64_t);
@@ -175,7 +184,8 @@ decode QUADRANT default Unknown::unknown() {
imm = CIMM5 | (CIMM1 << 5);
}}, {{
if (imm == 0) {
- fault = make_shared<IllegalInstFault>("immediate = 0");
+ fault = make_shared<IllegalInstFault>("immediate = 0",
+ machInst);
}
Rp1_sd = Rp1_sd >> imm;
}}, uint64_t);
@@ -246,10 +256,12 @@ decode QUADRANT default Unknown::unknown() {
imm = CIMM5 | (CIMM1 << 5);
}}, {{
if (imm == 0) {
- fault = make_shared<IllegalInstFault>("immediate = 0");
+ fault = make_shared<IllegalInstFault>("immediate = 0",
+ machInst);
}
if (RC1 == 0) {
- fault = make_shared<IllegalInstFault>("source reg x0");
+ fault = make_shared<IllegalInstFault>("source reg x0",
+ machInst);
}
Rc1 = Rc1 << imm;
}}, uint64_t);
@@ -269,7 +281,8 @@ decode QUADRANT default Unknown::unknown() {
CIMM5<1:0> << 6;
}}, {{
if (RC1 == 0) {
- fault = make_shared<IllegalInstFault>("source reg x0");
+ fault = make_shared<IllegalInstFault>("source reg x0",
+ machInst);
}
Rc1_sd = Mem_sw;
}}, {{
@@ -281,7 +294,8 @@ decode QUADRANT default Unknown::unknown() {
CIMM5<2:0> << 6;
}}, {{
if (RC1 == 0) {
- fault = make_shared<IllegalInstFault>("source reg x0");
+ fault = make_shared<IllegalInstFault>("source reg x0",
+ machInst);
}
Rc1_sd = Mem_sd;
}}, {{
@@ -292,13 +306,15 @@ decode QUADRANT default Unknown::unknown() {
0x0: decode RC2 {
0x0: Jump::c_jr({{
if (RC1 == 0) {
- fault = make_shared<IllegalInstFault>("source reg x0");
+ fault = make_shared<IllegalInstFault>("source reg x0",
+ machInst);
}
NPC = Rc1;
}}, IsIndirectControl, IsUncondControl, IsCall);
default: CROp::c_mv({{
if (RC1 == 0) {
- fault = make_shared<IllegalInstFault>("source reg x0");
+ fault = make_shared<IllegalInstFault>("source reg x0",
+ machInst);
}
Rc1 = Rc2;
}});
@@ -306,15 +322,17 @@ decode QUADRANT default Unknown::unknown() {
0x1: decode RC1 {
0x0: SystemOp::c_ebreak({{
if (RC2 != 0) {
- fault = make_shared<IllegalInstFault>("source reg x1");
+ fault = make_shared<IllegalInstFault>("source reg x1",
+ machInst);
}
- fault = make_shared<BreakpointFault>();
+ fault = make_shared<BreakpointFault>(xc->pcState());
}}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
default: decode RC2 {
0x0: Jump::c_jalr({{
if (RC1 == 0) {
fault = make_shared<IllegalInstFault>
- ("source reg x0");
+ ("source reg x0",
+ machInst);
}
ra = NPC;
NPC = Rc1;
@@ -1250,7 +1268,8 @@ decode QUADRANT default Unknown::unknown() {
}
0x20: fcvt_s_d({{
if (CONV_SGN != 1) {
- fault = make_shared<IllegalInstFault>("CONV_SGN != 1");
+ fault = make_shared<IllegalInstFault>("CONV_SGN != 1",
+ machInst);
}
float fd;
if (issignalingnan(Fs1)) {
@@ -1263,7 +1282,8 @@ decode QUADRANT default Unknown::unknown() {
}}, FloatCvtOp);
0x21: fcvt_d_s({{
if (CONV_SGN != 0) {
- fault = make_shared<IllegalInstFault>("CONV_SGN != 0");
+ fault = make_shared<IllegalInstFault>("CONV_SGN != 0",
+ machInst);
}
uint32_t temp;
float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
@@ -1277,7 +1297,8 @@ decode QUADRANT default Unknown::unknown() {
}}, FloatCvtOp);
0x2c: fsqrt_s({{
if (RS2 != 0) {
- fault = make_shared<IllegalInstFault>("source reg x1");
+ fault = make_shared<IllegalInstFault>("source reg x1",
+ machInst);
}
uint32_t temp;
float fs1 = reinterpret_cast<float&>(temp = Fs1_bits);
@@ -1291,7 +1312,8 @@ decode QUADRANT default Unknown::unknown() {
}}, FloatSqrtOp);
0x2d: fsqrt_d({{
if (RS2 != 0) {
- fault = make_shared<IllegalInstFault>("source reg x1");
+ fault = make_shared<IllegalInstFault>("source reg x1",
+ machInst);
}
Fd = sqrt(Fs1);
}}, FloatSqrtOp);
@@ -1690,10 +1712,11 @@ decode QUADRANT default Unknown::unknown() {
}}, IsSerializeAfter, IsNonSpeculative, IsSyscall,
No_OpClass);
0x1: ebreak({{
- fault = make_shared<BreakpointFault>();
+ fault = make_shared<BreakpointFault>(xc->pcState());
}}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
0x100: eret({{
- fault = make_shared<UnimplementedFault>("eret");
+ fault = make_shared<UnimplementedFault>("eret",
+ machInst);
}}, No_OpClass);
}
}
diff --git a/src/arch/riscv/isa/formats/fp.isa b/src/arch/riscv/isa/formats/fp.isa
index 1f08ca512..5f067218c 100644
--- a/src/arch/riscv/isa/formats/fp.isa
+++ b/src/arch/riscv/isa/formats/fp.isa
@@ -57,7 +57,7 @@ def template FloatExecute {{
break;
case 0x4:
// Round to nearest, ties to max magnitude not implemented
- fault = make_shared<IllegalFrmFault>(ROUND_MODE);
+ fault = make_shared<IllegalFrmFault>(ROUND_MODE, machInst);
break;
case 0x7: {
uint8_t frm = xc->readMiscReg(MISCREG_FRM);
@@ -76,16 +76,17 @@ def template FloatExecute {{
break;
case 0x4:
// Round to nearest, ties to max magnitude not implemented
- fault = make_shared<IllegalFrmFault>(ROUND_MODE);
+ fault = make_shared<IllegalFrmFault>(ROUND_MODE, machInst);
break;
default:
- fault = std::make_shared<IllegalFrmFault>(frm);
+ fault = std::make_shared<IllegalFrmFault>(frm, machInst);
break;
}
break;
}
default:
- fault = std::make_shared<IllegalFrmFault>(ROUND_MODE);
+ fault = std::make_shared<IllegalFrmFault>(ROUND_MODE,
+ machInst);
break;
}
diff --git a/src/arch/riscv/isa/formats/standard.isa b/src/arch/riscv/isa/formats/standard.isa
index e69ad7ee5..e9539fe52 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -231,7 +231,7 @@ def template CSRExecute {{
olddata = xc->readMiscReg(CSRData.at(csr).physIndex);
} else {
std::string error = csprintf("Illegal CSR index %#x\n", csr);
- fault = make_shared<IllegalInstFault>(error);
+ fault = make_shared<IllegalInstFault>(error, machInst);
olddata = 0;
}
break;
@@ -252,7 +252,7 @@ def template CSRExecute {{
if (bits(csr, 11, 10) == 0x3) {
std::string error = csprintf("CSR %s is read-only\n",
CSRData.at(csr).name);
- fault = make_shared<IllegalInstFault>(error);
+ fault = make_shared<IllegalInstFault>(error, machInst);
} else {
DPRINTF(RiscvMisc, "Writing %#x to CSR %s.\n", data,
CSRData.at(csr).name);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-04 21:33:30 +0000