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-rw-r--r--src/arch/riscv/isa/decoder.isa10
-rw-r--r--src/arch/riscv/isa/formats/fp.isa8
2 files changed, 12 insertions, 6 deletions
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 4f4ef7636..0e5567ac3 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -42,7 +42,8 @@ decode QUADRANT default Unknown::unknown() {
CIMM8<7:6> << 4 |
CIMM8<5:2> << 6;
}}, {{
- assert(imm != 0);
+ if (machInst == 0)
+ fault = make_shared<IllegalInstFault>("zero instruction");
Rp2 = sp + imm;
}});
format CompressedLoad {
@@ -103,7 +104,12 @@ decode QUADRANT default Unknown::unknown() {
if (CIMM1 > 0)
imm |= ~((uint64_t)0x1F);
}}, {{
- assert((RC1 == 0) == (imm == 0));
+ if ((RC1 == 0) != (imm == 0)) {
+ if (RC1 == 0) {
+ fault = make_shared<IllegalInstFault>("source reg x0");
+ } else // imm == 0
+ fault = make_shared<IllegalInstFault>("immediate = 0");
+ }
Rc1_sd = Rc1_sd + imm;
}});
0x1: c_addiw({{
diff --git a/src/arch/riscv/isa/formats/fp.isa b/src/arch/riscv/isa/formats/fp.isa
index 1f60b9b70..3de0bb2ff 100644
--- a/src/arch/riscv/isa/formats/fp.isa
+++ b/src/arch/riscv/isa/formats/fp.isa
@@ -56,8 +56,8 @@ def template FloatExecute {{
std::fesetround(FE_UPWARD);
break;
case 0x4:
- panic("Round to nearest, "
- "ties to max magnitude not implemented.");
+ // Round to nearest, ties to max magnitude not implemented
+ fault = make_shared<IllegalFrmFault>(ROUND_MODE);
break;
case 0x7: {
uint8_t frm = xc->readMiscReg(MISCREG_FRM);
@@ -75,8 +75,8 @@ def template FloatExecute {{
std::fesetround(FE_UPWARD);
break;
case 0x4:
- panic("Round to nearest,"
- " ties to max magnitude not implemented.");
+ // Round to nearest, ties to max magnitude not implemented
+ fault = make_shared<IllegalFrmFault>(ROUND_MODE);
break;
default:
fault = std::make_shared<IllegalFrmFault>(frm);