diff options
Diffstat (limited to 'src/arch/riscv/isa')
| -rw-r--r-- | src/arch/riscv/isa/decoder.isa | 4 | ||||
| -rw-r--r-- | src/arch/riscv/isa/formats/mem.isa | 7 |
2 files changed, 8 insertions, 3 deletions
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa index d98f94629..eac0652c0 100644 --- a/src/arch/riscv/isa/decoder.isa +++ b/src/arch/riscv/isa/decoder.isa @@ -218,12 +218,12 @@ decode OPCODE default Unknown::unknown() { 0x3: decode AMOFUNCT { 0x2: LoadReserved::lr_d({{ Rd_sd = Mem_sd; - }}, aq=AQ, rl=RL); + }}, mem_flags=LLSC, aq=AQ, rl=RL); 0x3: StoreCond::sc_d({{ Mem = Rs2; }}, {{ Rd = result; - }}, aq=AQ, rl=RL); + }}, mem_flags=LLSC, inst_flags=IsStoreConditional, aq=AQ, rl=RL); format AtomicMemOp { 0x0: amoadd_d({{Rt_sd = Mem_sd;}}, {{ Mem_sd = Rs2_sd + Rt_sd; diff --git a/src/arch/riscv/isa/formats/mem.isa b/src/arch/riscv/isa/formats/mem.isa index bea649c04..69a72dfa8 100644 --- a/src/arch/riscv/isa/formats/mem.isa +++ b/src/arch/riscv/isa/formats/mem.isa @@ -363,6 +363,9 @@ def template StoreCondExecute {{ if (fault == NoFault) { fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, &result); + // RISC-V has the opposite convention gem5 has for success flags, + // so we invert the result here. + result = !result; } if (fault == NoFault) { @@ -385,7 +388,9 @@ def template StoreCondCompleteAcc {{ %(op_dest_decl)s; - uint64_t result = pkt->req->getExtraData(); + // RISC-V has the opposite convention gem5 has for success flags, + // so we invert the result here. + uint64_t result = !pkt->req->getExtraData(); if (fault == NoFault) { %(postacc_code)s; |