diff options
Diffstat (limited to 'src/arch/riscv/tlb.cc')
| -rw-r--r-- | src/arch/riscv/tlb.cc | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/src/arch/riscv/tlb.cc b/src/arch/riscv/tlb.cc index 0c5962ece..ffb135c5a 100644 --- a/src/arch/riscv/tlb.cc +++ b/src/arch/riscv/tlb.cc @@ -143,7 +143,7 @@ TLB::probeEntry(Addr vpn, uint8_t asn) const } inline Fault -TLB::checkCacheability(RequestPtr &req) +TLB::checkCacheability(const RequestPtr &req) { Addr VAddrUncacheable = 0xA0000000; // In MIPS, cacheability is controlled by certain bits of the virtual @@ -283,7 +283,7 @@ TLB::regStats() } Fault -TLB::translateInst(RequestPtr req, ThreadContext *tc) +TLB::translateInst(const RequestPtr &req, ThreadContext *tc) { if (FullSystem) panic("translateInst not implemented in RISC-V.\n"); @@ -298,7 +298,7 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc) } Fault -TLB::translateData(RequestPtr req, ThreadContext *tc, bool write) +TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write) { if (FullSystem) panic("translateData not implemented in RISC-V.\n"); @@ -324,7 +324,7 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write) } Fault -TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) +TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode) { if (mode == Execute) return translateInst(req, tc); @@ -333,7 +333,7 @@ TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) } void -TLB::translateTiming(RequestPtr req, ThreadContext *tc, +TLB::translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode) { assert(translation); @@ -341,7 +341,8 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc, } Fault -TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const +TLB::finalizePhysical(const RequestPtr &req, + ThreadContext *tc, Mode mode) const { return NoFault; } |