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-rw-r--r--src/arch/riscv/tlb.hh16
1 files changed, 7 insertions, 9 deletions
diff --git a/src/arch/riscv/tlb.hh b/src/arch/riscv/tlb.hh
index 92d66f137..ce63fd33a 100644
--- a/src/arch/riscv/tlb.hh
+++ b/src/arch/riscv/tlb.hh
@@ -111,15 +111,13 @@ class TLB : public BaseTLB
void regStats() override;
- Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
- void translateTiming(RequestPtr req, ThreadContext *tc,
- Translation *translation, Mode mode);
-
- /** Function stub for CheckerCPU compilation issues. RISC-V does not
- * support the Checker model at the moment.
- */
- Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
- Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
+ Fault translateAtomic(
+ RequestPtr req, ThreadContext *tc, Mode mode) override;
+ void translateTiming(
+ RequestPtr req, ThreadContext *tc,
+ Translation *translation, Mode mode) override;
+ Fault finalizePhysical(
+ RequestPtr req, ThreadContext *tc, Mode mode) const override;
private:
Fault translateInst(RequestPtr req, ThreadContext *tc);