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-rw-r--r--src/arch/riscv/tlb.hh13
1 files changed, 7 insertions, 6 deletions
diff --git a/src/arch/riscv/tlb.hh b/src/arch/riscv/tlb.hh
index ce63fd33a..5d6c9dfc0 100644
--- a/src/arch/riscv/tlb.hh
+++ b/src/arch/riscv/tlb.hh
@@ -103,7 +103,7 @@ class TLB : public BaseTLB
// static helper functions... really
static bool validVirtualAddress(Addr vaddr);
- static Fault checkCacheability(RequestPtr &req);
+ static Fault checkCacheability(const RequestPtr &req);
// Checkpointing
void serialize(CheckpointOut &cp) const override;
@@ -112,16 +112,17 @@ class TLB : public BaseTLB
void regStats() override;
Fault translateAtomic(
- RequestPtr req, ThreadContext *tc, Mode mode) override;
+ const RequestPtr &req, ThreadContext *tc, Mode mode) override;
void translateTiming(
- RequestPtr req, ThreadContext *tc,
+ const RequestPtr &req, ThreadContext *tc,
Translation *translation, Mode mode) override;
Fault finalizePhysical(
- RequestPtr req, ThreadContext *tc, Mode mode) const override;
+ const RequestPtr &req,
+ ThreadContext *tc, Mode mode) const override;
private:
- Fault translateInst(RequestPtr req, ThreadContext *tc);
- Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
+ Fault translateInst(const RequestPtr &req, ThreadContext *tc);
+ Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write);
};
}