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-rw-r--r--src/arch/riscv/types.hh6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/arch/riscv/types.hh b/src/arch/riscv/types.hh
index 80f3c8652..976a9e70e 100644
--- a/src/arch/riscv/types.hh
+++ b/src/arch/riscv/types.hh
@@ -12,6 +12,9 @@
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
+ * Copyright (c) 2016 The University of Virginia
+ * All rights reserved.
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
@@ -37,6 +40,7 @@
*
* Authors: Andreas Hansson
* Sven Karlsson
+ * Alec Roelke
*/
#ifndef __ARCH_RISCV_TYPES_HH__
@@ -49,7 +53,7 @@ namespace RiscvISA
typedef uint32_t MachInst;
typedef uint64_t ExtMachInst;
-typedef GenericISA::SimplePCState<MachInst> PCState;
+typedef GenericISA::UPCState<MachInst> PCState;
}