diff options
Diffstat (limited to 'src/arch/riscv')
-rw-r--r-- | src/arch/riscv/isa.hh | 12 | ||||
-rw-r--r-- | src/arch/riscv/registers.hh | 10 |
2 files changed, 22 insertions, 0 deletions
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh index 3f2412303..578057aa0 100644 --- a/src/arch/riscv/isa.hh +++ b/src/arch/riscv/isa.hh @@ -97,6 +97,18 @@ class ISA : public SimObject return reg; } + int + flattenVecIndex(int reg) const + { + return reg; + } + + int + flattenVecElemIndex(int reg) const + { + return reg; + } + // dummy int flattenCCIndex(int reg) const diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh index 2666784e5..6ae1c1691 100644 --- a/src/arch/riscv/registers.hh +++ b/src/arch/riscv/registers.hh @@ -51,6 +51,7 @@ #include <string> #include "arch/generic/types.hh" +#include "arch/generic/vec_reg.hh" #include "arch/isa_traits.hh" #include "arch/riscv/generated/max_inst_regs.hh" #include "base/types.hh" @@ -67,10 +68,19 @@ typedef double FloatReg; typedef uint8_t CCReg; // Not applicable to Riscv typedef uint64_t MiscReg; +// dummy typedefs since we don't have vector regs +const unsigned NumVecElemPerVecReg = 2; +using VecElem = uint32_t; +using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>; +using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>; +using VecRegContainer = VecReg::Container; + const int NumIntArchRegs = 32; const int NumMicroIntRegs = 1; const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs; const int NumFloatRegs = 32; +// This has to be one to prevent warnings that are treated as errors +const unsigned NumVecRegs = 1; const int NumCCRegs = 0; const int NumMiscRegs = 4096; |