diff options
Diffstat (limited to 'src/arch/riscv')
| -rw-r--r-- | src/arch/riscv/isa/base.isa | 63 | ||||
| -rw-r--r-- | src/arch/riscv/isa/formats/amo.isa | 24 | ||||
| -rw-r--r-- | src/arch/riscv/isa/formats/basic.isa | 7 | ||||
| -rw-r--r-- | src/arch/riscv/isa/formats/mem.isa | 26 | ||||
| -rw-r--r-- | src/arch/riscv/isa/formats/standard.isa | 6 | ||||
| -rw-r--r-- | src/arch/riscv/isa/formats/unknown.isa | 2 | ||||
| -rw-r--r-- | src/arch/riscv/isa/includes.isa | 1 | ||||
| -rw-r--r-- | src/arch/riscv/isa/main.isa | 6 | ||||
| -rw-r--r-- | src/arch/riscv/isa/micro.isa | 114 | ||||
| -rw-r--r-- | src/arch/riscv/static_inst.hh | 139 |
10 files changed, 159 insertions, 229 deletions
diff --git a/src/arch/riscv/isa/base.isa b/src/arch/riscv/isa/base.isa deleted file mode 100644 index d54d7940b..000000000 --- a/src/arch/riscv/isa/base.isa +++ /dev/null @@ -1,63 +0,0 @@ -// -*- mode:c++ -*- - -// Copyright (c) 2015 RISC-V Foundation -// Copyright (c) 2016 The University of Virginia -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer; -// redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution; -// neither the name of the copyright holders nor the names of its -// contributors may be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// Authors: Maxwell Walter -// Alec Roelke - -//////////////////////////////////////////////////////////////////// -// -// Base class for Riscv instructions, and some support functions -// - -//Outputs to decoder.hh -output header {{ - using namespace RiscvISA; - - /** - * Base class for all RISC-V static instructions. - */ - class RiscvStaticInst : public StaticInst - { - protected: - // Constructor - RiscvStaticInst(const char *mnem, MachInst _machInst, - OpClass __opClass) : StaticInst(mnem, _machInst, __opClass) - {} - - virtual std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0; - - public: - void - advancePC(RiscvISA::PCState &pc) const - { - pc.advance(); - } - }; -}}; diff --git a/src/arch/riscv/isa/formats/amo.isa b/src/arch/riscv/isa/formats/amo.isa index 983c1f4cc..80a5faa19 100644 --- a/src/arch/riscv/isa/formats/amo.isa +++ b/src/arch/riscv/isa/formats/amo.isa @@ -148,13 +148,11 @@ def template AtomicMemOpDeclare {{ // Constructor %(class_name)sLoad(ExtMachInst machInst, %(class_name)s *_p); - %(BasicExecDeclare)s - - %(EACompDeclare)s - - %(InitiateAccDeclare)s - - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault eaComp(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const; }; class %(class_name)sStore : public %(base_class)sMicro @@ -163,13 +161,11 @@ def template AtomicMemOpDeclare {{ // Constructor %(class_name)sStore(ExtMachInst machInst, %(class_name)s *_p); - %(BasicExecDeclare)s - - %(EACompDeclare)s - - %(InitiateAccDeclare)s - - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault eaComp(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const; }; }; }}; diff --git a/src/arch/riscv/isa/formats/basic.isa b/src/arch/riscv/isa/formats/basic.isa index 2d27fd8b5..bb8401e3d 100644 --- a/src/arch/riscv/isa/formats/basic.isa +++ b/src/arch/riscv/isa/formats/basic.isa @@ -30,11 +30,6 @@ // Authors: Maxwell Walter // Alec Roelke -// Declarations for execute() methods. -def template BasicExecDeclare {{ - Fault execute(ExecContext *, Trace::InstRecord *) const; -}}; - // Basic instruction class declaration template. def template BasicDeclare {{ // @@ -45,7 +40,7 @@ def template BasicDeclare {{ public: /// Constructor. %(class_name)s(MachInst machInst); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; using %(base_class)s::generateDisassembly; }; }}; diff --git a/src/arch/riscv/isa/formats/mem.isa b/src/arch/riscv/isa/formats/mem.isa index 5f469dc8d..bce76c4d5 100644 --- a/src/arch/riscv/isa/formats/mem.isa +++ b/src/arch/riscv/isa/formats/mem.isa @@ -109,31 +109,13 @@ def template LoadStoreDeclare {{ /// Constructor. %(class_name)s(ExtMachInst machInst); - %(BasicExecDeclare)s - - %(EACompDeclare)s - - %(InitiateAccDeclare)s - - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault eaComp(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; }; }}; -def template EACompDeclare {{ - Fault - eaComp(ExecContext *, Trace::InstRecord *) const; -}}; - -def template InitiateAccDeclare {{ - Fault - initiateAcc(ExecContext *, Trace::InstRecord *) const; -}}; - - -def template CompleteAccDeclare {{ - Fault - completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; -}}; def template LoadStoreConstructor {{ %(class_name)s::%(class_name)s(ExtMachInst machInst): diff --git a/src/arch/riscv/isa/formats/standard.isa b/src/arch/riscv/isa/formats/standard.isa index 70d6ada33..35c3fa878 100644 --- a/src/arch/riscv/isa/formats/standard.isa +++ b/src/arch/riscv/isa/formats/standard.isa @@ -184,7 +184,7 @@ def template ImmDeclare {{ public: /// Constructor. %(class_name)s(MachInst machInst); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const override; }; @@ -240,7 +240,7 @@ def template BranchDeclare {{ public: /// Constructor. %(class_name)s(MachInst machInst); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const override; @@ -299,7 +299,7 @@ def template JumpDeclare {{ public: /// Constructor. %(class_name)s(MachInst machInst); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const override; diff --git a/src/arch/riscv/isa/formats/unknown.isa b/src/arch/riscv/isa/formats/unknown.isa index aaab21137..b6d76497d 100644 --- a/src/arch/riscv/isa/formats/unknown.isa +++ b/src/arch/riscv/isa/formats/unknown.isa @@ -51,7 +51,7 @@ output header {{ flags[IsNonSpeculative] = true; } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; diff --git a/src/arch/riscv/isa/includes.isa b/src/arch/riscv/isa/includes.isa index 82d1794fd..c172d0300 100644 --- a/src/arch/riscv/isa/includes.isa +++ b/src/arch/riscv/isa/includes.isa @@ -42,6 +42,7 @@ output header {{ #include <tuple> #include <vector> +#include "arch/riscv/static_inst.hh" #include "cpu/static_inst.hh" #include "mem/packet.hh" #include "mem/request.hh" diff --git a/src/arch/riscv/isa/main.isa b/src/arch/riscv/isa/main.isa index 58ec22341..3ffb3e6b4 100644 --- a/src/arch/riscv/isa/main.isa +++ b/src/arch/riscv/isa/main.isa @@ -53,12 +53,6 @@ namespace RiscvISA; //Include the operand_types and operand definitions ##include "operands.isa" -//Include the base class for riscv instructions, and some support code -##include "base.isa" - -// Include the base class for instructions with micro code -##include "micro.isa" - //Include the definitions for the instruction formats ##include "formats/formats.isa" diff --git a/src/arch/riscv/isa/micro.isa b/src/arch/riscv/isa/micro.isa deleted file mode 100644 index 61be076b0..000000000 --- a/src/arch/riscv/isa/micro.isa +++ /dev/null @@ -1,114 +0,0 @@ -// -*- mode:c++ -*- - -// Copyright (c) 2015 Riscv Developers -// Copyright (c) 2016 The University of Virginia -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer; -// redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution; -// neither the name of the copyright holders nor the names of its -// contributors may be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// Authors: Alec Roelke - -def template MacroInitiateAcc {{ - Fault initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const - { - panic("Tried to execute a macroop directly!\n"); - return NoFault; - } -}}; - -def template MacroCompleteAcc {{ - Fault completeAcc(PacketPtr pkt, ExecContext *xc, - Trace::InstRecord *traceData) const - { - panic("Tried to execute a macroop directly!\n"); - return NoFault; - } -}}; - -def template MacroExecute {{ - Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const - { - panic("Tried to execute a macroop directly!\n"); - return NoFault; - } -}}; - -output header {{ - /** - * Base class for all RISC-V Macroops - */ - class RiscvMacroInst : public RiscvStaticInst - { - protected: - std::vector<StaticInstPtr> microops; - - // Constructor - RiscvMacroInst(const char *mnem, ExtMachInst _machInst, - OpClass __opClass) - : RiscvStaticInst(mnem, _machInst, __opClass) - { - flags[IsMacroop] = true; - } - - ~RiscvMacroInst() - { - microops.clear(); - } - - StaticInstPtr fetchMicroop(MicroPC upc) const - { - return microops[upc]; - } - - %(MacroInitiateAcc)s - - %(MacroCompleteAcc)s - - %(MacroExecute)s - }; - - /** - * Base class for all RISC-V Microops - */ - class RiscvMicroInst : public RiscvStaticInst - { - protected: - // Constructor - RiscvMicroInst(const char *mnem, ExtMachInst _machInst, - OpClass __opClass) - : RiscvStaticInst(mnem, _machInst, __opClass) - { - flags[IsMicroop] = true; - } - - void advancePC(RiscvISA::PCState &pcState) const - { - if (flags[IsLastMicroop]) { - pcState.uEnd(); - } else { - pcState.uAdvance(); - } - } - }; -}}; diff --git a/src/arch/riscv/static_inst.hh b/src/arch/riscv/static_inst.hh new file mode 100644 index 000000000..bdcdee74a --- /dev/null +++ b/src/arch/riscv/static_inst.hh @@ -0,0 +1,139 @@ +// -*- mode:c++ -*- + +// Copyright (c) 2015 RISC-V Foundation +// Copyright (c) 2016 The University of Virginia +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer; +// redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution; +// neither the name of the copyright holders nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Authors: Maxwell Walter +// Alec Roelke + +#ifndef __ARCH_RISCV_STATIC_INST_HH__ +#define __ARCH_RISCV_STATIC_INST_HH__ + +//////////////////////////////////////////////////////////////////// +// +// Base class for Riscv instructions, and some support functions +// + +namespace RiscvISA { + +/** + * Base class for all RISC-V static instructions. + */ +class RiscvStaticInst : public StaticInst +{ + protected: + // Constructor + RiscvStaticInst(const char *mnem, MachInst _machInst, + OpClass __opClass) : StaticInst(mnem, _machInst, __opClass) + {} + + virtual std::string + generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0; + + public: + void + advancePC(RiscvISA::PCState &pc) const + { + pc.advance(); + } +}; + +/** + * Base class for all RISC-V Macroops + */ +class RiscvMacroInst : public RiscvStaticInst +{ + protected: + std::vector<StaticInstPtr> microops; + + // Constructor + RiscvMacroInst(const char *mnem, ExtMachInst _machInst, + OpClass __opClass) : + RiscvStaticInst(mnem, _machInst, __opClass) + { + flags[IsMacroop] = true; + } + + ~RiscvMacroInst() + { + microops.clear(); + } + + StaticInstPtr + fetchMicroop(MicroPC upc) const + { + return microops[upc]; + } + + Fault + initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const + { + panic("Tried to execute a macroop directly!\n"); + } + + Fault + completeAcc(PacketPtr pkt, ExecContext *xc, + Trace::InstRecord *traceData) const + { + panic("Tried to execute a macroop directly!\n"); + } + + Fault + execute(ExecContext *xc, Trace::InstRecord *traceData) const + { + panic("Tried to execute a macroop directly!\n"); + } +}; + +/** + * Base class for all RISC-V Microops + */ +class RiscvMicroInst : public RiscvStaticInst +{ + protected: + // Constructor + RiscvMicroInst(const char *mnem, ExtMachInst _machInst, + OpClass __opClass) : + RiscvStaticInst(mnem, _machInst, __opClass) + { + flags[IsMicroop] = true; + } + + void + advancePC(RiscvISA::PCState &pcState) const + { + if (flags[IsLastMicroop]) { + pcState.uEnd(); + } else { + pcState.uAdvance(); + } + } +}; + +} + +#endif // __ARCH_RISCV_STATIC_INST_HH__ |