3 files changed, 4 insertions, 4 deletions

diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index a67274221..7f7cefee9 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -65,7 +65,7 @@ using RiscvISAInst::MaxInstDestRegs;
 const int MaxMiscDestRegs = 1;
 
 typedef RegVal IntReg;
-typedef RegVal FloatRegBits;
+typedef RegVal FloatReg;
 typedef uint8_t CCReg; // Not applicable to Riscv
 typedef RegVal MiscReg;
 
diff --git a/src/arch/riscv/remote_gdb.cc b/src/arch/riscv/remote_gdb.cc
index 6d56a93b6..fe339ffc8 100644
--- a/src/arch/riscv/remote_gdb.cc
+++ b/src/arch/riscv/remote_gdb.cc
@@ -168,7 +168,7 @@ RemoteGDB::RiscvGdbRegCache::getRegs(ThreadContext *context)
         r.gpr[i] = context->readIntReg(i);
     r.pc = context->pcState().pc();
     for (int i = 0; i < NumFloatRegs; i++)
-        r.fpr[i] = context->readFloatRegBits(i);
+        r.fpr[i] = context->readFloatReg(i);
 
     r.csr_base = context->readMiscReg(0);
     r.fflags = context->readMiscReg(CSR_FFLAGS);
@@ -186,7 +186,7 @@ RemoteGDB::RiscvGdbRegCache::setRegs(ThreadContext *context) const
         context->setIntReg(i, r.gpr[i]);
     context->pcState(r.pc);
     for (int i = 0; i < NumFloatRegs; i++)
-        context->setFloatRegBits(i, r.fpr[i]);
+        context->setFloatReg(i, r.fpr[i]);
 
     context->setMiscReg(0, r.csr_base);
     context->setMiscReg(CSR_FFLAGS, r.fflags);
diff --git a/src/arch/riscv/remote_gdb.hh b/src/arch/riscv/remote_gdb.hh
index 739cb5a3e..adb438d24 100644
--- a/src/arch/riscv/remote_gdb.hh
+++ b/src/arch/riscv/remote_gdb.hh
@@ -61,7 +61,7 @@ class RemoteGDB : public BaseRemoteGDB
         struct {
             IntReg gpr[NumIntArchRegs];
             IntReg pc;
-            FloatRegBits fpr[NumFloatRegs];
+            FloatReg fpr[NumFloatRegs];
 
             MiscReg csr_base;
             uint32_t fflags;