1 files changed, 94 insertions, 0 deletions
diff --git a/src/arch/sparc/insts/mem.cc b/src/arch/sparc/insts/mem.cc
new file mode 100644
index 000000000..a78ea6697
--- /dev/null
+++ b/src/arch/sparc/insts/mem.cc
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2006-2007 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ *          Gabe Black
+ *          Steve Reinhardt
+ */
+
+#include "arch/sparc/insts/mem.hh"
+
+namespace SparcISA
+{
+
+std::string
+Mem::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    std::stringstream response;
+    bool load = flags[IsLoad];
+    bool store = flags[IsStore];
+
+    printMnemonic(response, mnemonic);
+    if (store) {
+        printReg(response, _srcRegIdx[0]);
+        ccprintf(response, ", ");
+    }
+    ccprintf(response, "[");
+    if (_srcRegIdx[!store ? 0 : 1].index() != 0) {
+        printSrcReg(response, !store ? 0 : 1);
+        ccprintf(response, " + ");
+    }
+    printSrcReg(response, !store ? 1 : 2);
+    ccprintf(response, "]");
+    if (load) {
+        ccprintf(response, ", ");
+        printReg(response, _destRegIdx[0]);
+    }
+
+    return response.str();
+}
+
+std::string
+MemImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    std::stringstream response;
+    bool load = flags[IsLoad];
+    bool save = flags[IsStore];
+
+    printMnemonic(response, mnemonic);
+    if (save) {
+        printReg(response, _srcRegIdx[0]);
+        ccprintf(response, ", ");
+    }
+    ccprintf(response, "[");
+    if (_srcRegIdx[!save ? 0 : 1].index() != 0) {
+        printReg(response, _srcRegIdx[!save ? 0 : 1]);
+        ccprintf(response, " + ");
+    }
+    if (imm >= 0)
+        ccprintf(response, "%#x]", imm);
+    else
+        ccprintf(response, "-%#x]", -imm);
+    if (load) {
+        ccprintf(response, ", ");
+        printReg(response, _destRegIdx[0]);
+    }
+
+    return response.str();
+}
+
+}