diff options
Diffstat (limited to 'src/arch/sparc/insts')
| -rw-r--r-- | src/arch/sparc/insts/SConscript | 1 | ||||
| -rw-r--r-- | src/arch/sparc/insts/priv.cc | 101 | ||||
| -rw-r--r-- | src/arch/sparc/insts/priv.hh | 113 |
3 files changed, 215 insertions, 0 deletions
diff --git a/src/arch/sparc/insts/SConscript b/src/arch/sparc/insts/SConscript index 94996f6b2..1e2797351 100644 --- a/src/arch/sparc/insts/SConscript +++ b/src/arch/sparc/insts/SConscript @@ -32,4 +32,5 @@ Import('*') if env['TARGET_ISA'] == 'sparc': + Source('priv.cc') Source('static_inst.cc') diff --git a/src/arch/sparc/insts/priv.cc b/src/arch/sparc/insts/priv.cc new file mode 100644 index 000000000..ce6d04446 --- /dev/null +++ b/src/arch/sparc/insts/priv.cc @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2006-2007 The Regents of The University of Michigan + * All rights reserved + * Copyright 2017 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + * Gabe Black + * Steve Reinhardt + */ + +#include "arch/sparc/insts/priv.hh" + +namespace SparcISA +{ + +std::string +Priv::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + std::stringstream response; + + printMnemonic(response, mnemonic); + + return response.str(); +} + +std::string +RdPriv::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + std::stringstream response; + + printMnemonic(response, mnemonic); + + ccprintf(response, " %%%s, ", regName); + printDestReg(response, 0); + + return response.str(); +} + +std::string +WrPriv::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + std::stringstream response; + + printMnemonic(response, mnemonic); + + ccprintf(response, " "); + // If the first reg is %g0, don't print it. + // This improves readability + if (_srcRegIdx[0].index() != 0) { + printSrcReg(response, 0); + ccprintf(response, ", "); + } + printSrcReg(response, 1); + ccprintf(response, ", %%%s", regName); + + return response.str(); +} + +std::string +WrPrivImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + std::stringstream response; + + printMnemonic(response, mnemonic); + + ccprintf(response, " "); + // If the first reg is %g0, don't print it. + // This improves readability + if (_srcRegIdx[0].index() != 0) { + printSrcReg(response, 0); + ccprintf(response, ", "); + } + ccprintf(response, "%#x, %%%s", imm, regName); + + return response.str(); +} + +} diff --git a/src/arch/sparc/insts/priv.hh b/src/arch/sparc/insts/priv.hh new file mode 100644 index 000000000..6530d09f8 --- /dev/null +++ b/src/arch/sparc/insts/priv.hh @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2006-2007 The Regents of The University of Michigan + * All rights reserved + * Copyright 2017 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + * Gabe Black + * Steve Reinhardt + */ + +#ifndef __ARCH_SPARC_INSTS_PRIV_HH__ +#define __ARCH_SPARC_INSTS_PRIV_HH__ + +#include "arch/sparc/insts/static_inst.hh" + +namespace SparcISA +{ + +/** + * Base class for privelege mode operations. + */ +class Priv : public SparcStaticInst +{ + protected: + using SparcStaticInst::SparcStaticInst; + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; +}; + +class PrivReg : public Priv +{ + protected: + PrivReg(const char *mnem, ExtMachInst _machInst, + OpClass __opClass, char const * _regName) : + Priv(mnem, _machInst, __opClass), regName(_regName) + {} + + char const *regName; +}; + +// This class is for instructions that explicitly read control +// registers. It provides a special generateDisassembly function. +class RdPriv : public PrivReg +{ + protected: + using PrivReg::PrivReg; + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; +}; + +// This class is for instructions that explicitly write control +// registers. It provides a special generateDisassembly function. +class WrPriv : public PrivReg +{ + protected: + using PrivReg::PrivReg; + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; +}; + +/** + * Base class for privelege mode operations with immediates. + */ +class PrivImm : public Priv +{ + protected: + // Constructor + PrivImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : + Priv(mnem, _machInst, __opClass), imm(bits(_machInst, 12, 0)) + {} + + int32_t imm; +}; + +// This class is for instructions that explicitly write control +// registers. It provides a special generateDisassembly function. +class WrPrivImm : public PrivImm +{ + protected: + // Constructor + WrPrivImm(const char *mnem, ExtMachInst _machInst, + OpClass __opClass, char const *_regName) : + PrivImm(mnem, _machInst, __opClass), regName(_regName) + {} + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + + char const *regName; +} +; +} + +#endif //__ARCH_SPARC_INSTS_PRIV_HH__ |