3 files changed, 18 insertions, 18 deletions

diff --git a/src/arch/sparc/isa/formats/mem/basicmem.isa b/src/arch/sparc/isa/formats/mem/basicmem.isa
index aa6c4cdea..e3c043cf3 100644
--- a/src/arch/sparc/isa/formats/mem/basicmem.isa
+++ b/src/arch/sparc/isa/formats/mem/basicmem.isa
@@ -72,22 +72,22 @@ let {{
         return (header_output, decoder_output, exec_output, decode_block)
 }};
 
-def format LoadAlt(code, asi, *opt_flags) {{
+def format LoadAlt(code, *opt_flags) {{
         code = filterDoubles(code)
         (header_output,
          decoder_output,
          exec_output,
          decode_block) = doMemFormat(code, LoadFuncs,
-            AlternateASIPrivFaultCheck, name, Name, asi, opt_flags)
+            AlternateASIPrivFaultCheck, name, Name, "EXT_ASI", opt_flags)
 }};
 
-def format StoreAlt(code, asi, *opt_flags) {{
+def format StoreAlt(code, *opt_flags) {{
         code = filterDoubles(code)
         (header_output,
          decoder_output,
          exec_output,
          decode_block) = doMemFormat(code, StoreFuncs,
-            AlternateASIPrivFaultCheck, name, Name, asi, opt_flags)
+            AlternateASIPrivFaultCheck, name, Name, "EXT_ASI", opt_flags)
 }};
 
 def format Load(code, *opt_flags) {{
@@ -108,12 +108,12 @@ def format Store(code, *opt_flags) {{
              StoreFuncs, '', name, Name, 0, opt_flags)
 }};
 
-def format TwinLoad(code, asi, *opt_flags) {{
+def format TwinLoad(code, *opt_flags) {{
         (header_output,
          decoder_output,
          exec_output,
          decode_block) = doMemFormat(code, LoadFuncs,
             AlternateASIPrivFaultCheck + TwinAlignmentFaultCheck,
-            name, Name, asi, opt_flags)
+            name, Name, "EXT_ASI", opt_flags)
 }};
 
diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa
index 5d36e5e41..020dc326f 100644
--- a/src/arch/sparc/isa/formats/mem/blockmem.isa
+++ b/src/arch/sparc/isa/formats/mem/blockmem.isa
@@ -273,7 +273,7 @@ def template BlockMemMicroConstructor {{
 
 let {{
 
-    def doBlockMemFormat(code, faultCode, execute, name, Name, asi, opt_flags):
+    def doBlockMemFormat(code, faultCode, execute, name, Name, opt_flags):
         # XXX Need to take care of pstate.hpriv as well. The lower ASIs
         # are split into ones that are available in priv and hpriv, and
         # those that are only available in hpriv
@@ -313,12 +313,12 @@ let {{
                     makeMicroName(name + "Imm", microPc),
                     makeMicroName(Name, microPc),
                     makeMicroName(Name + "Imm", microPc),
-                    asi, opt_flags);
+                    "EXT_ASI", opt_flags);
             faultCode = ''
         return (header_output, decoder_output, exec_output, decode_block)
 }};
 
-def format BlockLoad(code, asi, *opt_flags) {{
+def format BlockLoad(code, *opt_flags) {{
         code = filterDoubles(code)
         # We need to make sure to check the highest priority fault last.
         # That way, if other faults have been detected, they'll be overwritten
@@ -328,10 +328,10 @@ def format BlockLoad(code, asi, *opt_flags) {{
          decoder_output,
          exec_output,
          decode_block) = doBlockMemFormat(code, faultCode,
-             LoadFuncs, name, Name, asi, opt_flags)
+             LoadFuncs, name, Name, opt_flags)
 }};
 
-def format BlockStore(code, asi, *opt_flags) {{
+def format BlockStore(code, *opt_flags) {{
         code = filterDoubles(code)
         # We need to make sure to check the highest priority fault last.
         # That way, if other faults have been detected, they'll be overwritten
@@ -341,5 +341,5 @@ def format BlockStore(code, asi, *opt_flags) {{
          decoder_output,
          exec_output,
          decode_block) = doBlockMemFormat(code, faultCode,
-             StoreFuncs, name, Name, asi, opt_flags)
+             StoreFuncs, name, Name, opt_flags)
 }};
diff --git a/src/arch/sparc/isa/formats/mem/swap.isa b/src/arch/sparc/isa/formats/mem/swap.isa
index dde327f5c..2ebe9aa15 100644
--- a/src/arch/sparc/isa/formats/mem/swap.isa
+++ b/src/arch/sparc/isa/formats/mem/swap.isa
@@ -142,9 +142,9 @@ def format Swap(code, postacc_code, mem_flags, *opt_flags) {{
          ["IsStoreConditional"], postacc_code)
 }};
 
-def format SwapAlt(code, postacc_code, asi, mem_flags, *opt_flags) {{
+def format SwapAlt(code, postacc_code, mem_flags, *opt_flags) {{
     mem_flags = makeList(mem_flags)
-    mem_flags.append(asi)
+    mem_flags.append("EXT_ASI")
     flags = string.join(mem_flags, '|')
     (header_output,
      decoder_output,
@@ -155,7 +155,7 @@ def format SwapAlt(code, postacc_code, asi, mem_flags, *opt_flags) {{
 
 
 let {{
-    def doCasFormat(code, execute, faultCode, name, Name, asi, opt_flags, postacc_code = ''):
+    def doCasFormat(code, execute, faultCode, name, Name, mem_flags, opt_flags, postacc_code = ''):
         addrCalcReg = 'EA = Rs1;'
         iop = InstObjParams(name, Name, 'Mem',
                 {"code": code, "postacc_code" : postacc_code,
@@ -167,15 +167,15 @@ let {{
         microParams = {"code": code, "postacc_code" : postacc_code,
             "ea_code" : addrCalcReg, "fault_check" : faultCode,
             "EA_trunc" : TruncateEA}
-        exec_output = doSplitExecute(execute, name, Name, asi,
+        exec_output = doSplitExecute(execute, name, Name, mem_flags,
                 ["IsStoreConditional"], microParams);
         return (header_output, decoder_output, exec_output, decode_block)
 }};
 
 
-def format CasAlt(code, postacc_code, asi, mem_flags, *opt_flags) {{
+def format CasAlt(code, postacc_code, mem_flags, *opt_flags) {{
     mem_flags = makeList(mem_flags)
-    mem_flags.append(asi)
+    mem_flags.append("EXT_ASI")
     flags = string.join(mem_flags, '|')
     (header_output,
      decoder_output,