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Diffstat (limited to 'src/arch/sparc/isa/operands.isa')
| -rw-r--r-- | src/arch/sparc/isa/operands.isa | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa index 256f2fa43..2d1c3d3b9 100644 --- a/src/arch/sparc/isa/operands.isa +++ b/src/arch/sparc/isa/operands.isa @@ -62,6 +62,9 @@ def operands {{ 'Rd_prev': ('IntReg', 'udw', 'RD + NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 2), # The Rd from the next window 'Rd_next': ('IntReg', 'udw', 'RD + 2 * NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 3), + # For microcoded twin load instructions, RdTwin appears in the "code" + # for the instruction is replaced by RdLow or RdHigh by the format + # before it's processed by the iop. # The low (even) register of a two register pair 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 4), # The high (odd) register of a two register pair |