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-rw-r--r--src/arch/sparc/isa/operands.isa8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa
index 605816083..b01443d5b 100644
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -52,6 +52,14 @@ def operands {{
'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4),
'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5),
'Frd': ('FloatReg', 'df', 'RD', 'IsFloating', 10),
+ 'Frd_0': ('FloatReg', 'df', 'RD', 'IsFloating', 10),
+ 'Frd_1': ('FloatReg', 'df', 'RD + 1', 'IsFloating', 10),
+ 'Frd_2': ('FloatReg', 'df', 'RD + 2', 'IsFloating', 10),
+ 'Frd_3': ('FloatReg', 'df', 'RD + 3', 'IsFloating', 10),
+ 'Frd_4': ('FloatReg', 'df', 'RD + 4', 'IsFloating', 10),
+ 'Frd_5': ('FloatReg', 'df', 'RD + 5', 'IsFloating', 10),
+ 'Frd_6': ('FloatReg', 'df', 'RD + 6', 'IsFloating', 10),
+ 'Frd_7': ('FloatReg', 'df', 'RD + 7', 'IsFloating', 10),
'Frs1': ('FloatReg', 'df', 'RS1', 'IsFloating', 11),
'Frs2': ('FloatReg', 'df', 'RS2', 'IsFloating', 12),
'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 20),