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Diffstat (limited to 'src/arch/sparc/isa/operands.isa')
| -rw-r--r-- | src/arch/sparc/isa/operands.isa | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa index 80ed7362c..abb82f88c 100644 --- a/src/arch/sparc/isa/operands.isa +++ b/src/arch/sparc/isa/operands.isa @@ -57,6 +57,9 @@ def operands {{ # For clarity, descriptions that depend on unsigned behavior should # explicitly specify '.uq'. 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1), + # For microcoded twin load instructions, RdTwin appears in the "code" + # for the instruction and is replaced by RdLow or RdHigh by the format + # before it's processed by the iop. 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 2), 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 3), 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4), |