summaryrefslogtreecommitdiff
path: root/src/arch/sparc/isa
diff options
context:
space:
mode:
Diffstat (limited to 'src/arch/sparc/isa')
-rw-r--r--src/arch/sparc/isa/base.isa2
-rw-r--r--src/arch/sparc/isa/bitfields.isa4
-rw-r--r--src/arch/sparc/isa/decoder.isa312
-rw-r--r--src/arch/sparc/isa/formats.isa28
-rw-r--r--src/arch/sparc/isa/formats/basic.isa17
-rw-r--r--src/arch/sparc/isa/formats/branch.isa6
-rw-r--r--src/arch/sparc/isa/formats/formats.isa62
-rw-r--r--src/arch/sparc/isa/formats/integerop.isa12
-rw-r--r--src/arch/sparc/isa/formats/mem/basicmem.isa (renamed from src/arch/sparc/isa/formats/mem.isa)117
-rw-r--r--src/arch/sparc/isa/formats/mem/blockmem.isa337
-rw-r--r--src/arch/sparc/isa/formats/mem/mem.isa45
-rw-r--r--src/arch/sparc/isa/formats/mem/util.isa226
-rw-r--r--src/arch/sparc/isa/formats/micro.isa103
-rw-r--r--src/arch/sparc/isa/formats/priv.isa4
-rw-r--r--src/arch/sparc/isa/formats/unimp.isa147
-rw-r--r--src/arch/sparc/isa/includes.isa4
-rw-r--r--src/arch/sparc/isa/main.isa4
-rw-r--r--src/arch/sparc/isa/operands.isa34
18 files changed, 1290 insertions, 174 deletions
diff --git a/src/arch/sparc/isa/base.isa b/src/arch/sparc/isa/base.isa
index b518265aa..a4c022411 100644
--- a/src/arch/sparc/isa/base.isa
+++ b/src/arch/sparc/isa/base.isa
@@ -77,7 +77,7 @@ output header {{
protected:
// Constructor.
SparcStaticInst(const char *mnem,
- MachInst _machInst, OpClass __opClass)
+ ExtMachInst _machInst, OpClass __opClass)
: StaticInst(mnem, _machInst, __opClass)
{
}
diff --git a/src/arch/sparc/isa/bitfields.isa b/src/arch/sparc/isa/bitfields.isa
index 27f52fa29..372f5c4ef 100644
--- a/src/arch/sparc/isa/bitfields.isa
+++ b/src/arch/sparc/isa/bitfields.isa
@@ -76,3 +76,7 @@ def bitfield SIMM11 <10:0>;
def bitfield SIMM13 <12:0>;
def bitfield SW_TRAP <7:0>;
def bitfield X <12>;
+
+// Extended bitfields which aren't part of the actual instruction.
+
+def bitfield EXT_ASI <39:32>;
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index 1384b21a0..45d3616d9 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -441,7 +441,7 @@ decode OP default Unknown::unknown()
0x34: decode OPF{
format BasicOperate{
0x01: fmovs({{
- Frd.uw = Frs2.uw;
+ Frds.uw = Frs2s.uw;
//fsr.ftt = fsr.cexc = 0
Fsr &= ~(7 << 14);
Fsr &= ~(0x1F);
@@ -454,7 +454,7 @@ decode OP default Unknown::unknown()
}});
0x03: Trap::fmovq({{fault = new FpDisabled;}});
0x05: fnegs({{
- Frd.uw = Frs2.uw ^ (1UL << 31);
+ Frds.uw = Frs2s.uw ^ (1UL << 31);
//fsr.ftt = fsr.cexc = 0
Fsr &= ~(7 << 14);
Fsr &= ~(0x1F);
@@ -467,7 +467,7 @@ decode OP default Unknown::unknown()
}});
0x07: Trap::fnegq({{fault = new FpDisabled;}});
0x09: fabss({{
- Frd.uw = ((1UL << 31) - 1) & Frs2.uw;
+ Frds.uw = ((1UL << 31) - 1) & Frs2s.uw;
//fsr.ftt = fsr.cexc = 0
Fsr &= ~(7 << 14);
Fsr &= ~(0x1F);
@@ -479,55 +479,55 @@ decode OP default Unknown::unknown()
Fsr &= ~(0x1F);
}});
0x0B: Trap::fabsq({{fault = new FpDisabled;}});
- 0x29: fsqrts({{Frd.sf = sqrt(Frs2.sf);}});
+ 0x29: fsqrts({{Frds.sf = sqrt(Frs2s.sf);}});
0x2A: fsqrtd({{Frd.df = sqrt(Frs2.df);}});
0x2B: Trap::fsqrtq({{fault = new FpDisabled;}});
- 0x41: fadds({{Frd.sf = Frs1.sf + Frs2.sf;}});
+ 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}});
0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
0x43: Trap::faddq({{fault = new FpDisabled;}});
- 0x45: fsubs({{Frd.sf = Frs1.sf - Frs2.sf;}});
+ 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}});
0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}});
0x47: Trap::fsubq({{fault = new FpDisabled;}});
- 0x49: fmuls({{Frd.sf = Frs1.sf * Frs2.sf;}});
+ 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}});
0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}});
0x4B: Trap::fmulq({{fault = new FpDisabled;}});
- 0x4D: fdivs({{Frd.sf = Frs1.sf / Frs2.sf;}});
+ 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}});
0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}});
0x4F: Trap::fdivq({{fault = new FpDisabled;}});
- 0x69: fsmuld({{Frd.df = Frs1.sf * Frs2.sf;}});
+ 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}});
0x6E: Trap::fdmulq({{fault = new FpDisabled;}});
0x81: fstox({{
- Frd.df = (double)static_cast<int64_t>(Frs2.sf);
+ Frd.df = (double)static_cast<int64_t>(Frs2s.sf);
}});
0x82: fdtox({{
Frd.df = (double)static_cast<int64_t>(Frs2.df);
}});
0x83: Trap::fqtox({{fault = new FpDisabled;}});
0x84: fxtos({{
- Frd.sf = static_cast<float>((int64_t)Frs2.df);
+ Frds.sf = static_cast<float>((int64_t)Frs2.df);
}});
0x88: fxtod({{
Frd.df = static_cast<double>((int64_t)Frs2.df);
}});
0x8C: Trap::fxtoq({{fault = new FpDisabled;}});
0xC4: fitos({{
- Frd.sf = static_cast<float>((int32_t)Frs2.sf);
+ Frds.sf = static_cast<float>((int32_t)Frs2s.sf);
}});
- 0xC6: fdtos({{Frd.sf = Frs2.df;}});
+ 0xC6: fdtos({{Frds.sf = Frs2.df;}});
0xC7: Trap::fqtos({{fault = new FpDisabled;}});
0xC8: fitod({{
- Frd.df = static_cast<double>((int32_t)Frs2.sf);
+ Frd.df = static_cast<double>((int32_t)Frs2s.sf);
}});
- 0xC9: fstod({{Frd.df = Frs2.sf;}});
+ 0xC9: fstod({{Frd.df = Frs2s.sf;}});
0xCB: Trap::fqtod({{fault = new FpDisabled;}});
0xCC: Trap::fitoq({{fault = new FpDisabled;}});
0xCD: Trap::fstoq({{fault = new FpDisabled;}});
0xCE: Trap::fdtoq({{fault = new FpDisabled;}});
0xD1: fstoi({{
- Frd.sf = (float)static_cast<int32_t>(Frs2.sf);
+ Frds.sf = (float)static_cast<int32_t>(Frs2s.sf);
}});
0xD2: fdtoi({{
- Frd.sf = (float)static_cast<int32_t>(Frs2.df);
+ Frds.sf = (float)static_cast<int32_t>(Frs2.df);
}});
0xD3: Trap::fqtoi({{fault = new FpDisabled;}});
default: Trap::fpop1({{fault = new FpDisabled;}});
@@ -620,7 +620,7 @@ decode OP default Unknown::unknown()
0x56: Trap::fpsub32({{fault = new IllegalInstruction;}});
0x57: Trap::fpsub32s({{fault = new IllegalInstruction;}});
0x60: BasicOperate::fzero({{Frd.df = 0;}});
- 0x61: BasicOperate::fzeros({{Frd.sf = 0;}});
+ 0x61: BasicOperate::fzeros({{Frds.sf = 0;}});
0x62: Trap::fnor({{fault = new IllegalInstruction;}});
0x63: Trap::fnors({{fault = new IllegalInstruction;}});
0x64: Trap::fandnot2({{fault = new IllegalInstruction;}});
@@ -629,7 +629,7 @@ decode OP default Unknown::unknown()
Frd.df = (double)(~((uint64_t)Frs2.df));
}});
0x67: BasicOperate::fnot2s({{
- Frd.sf = (float)(~((uint32_t)Frs2.sf));
+ Frds.sf = (float)(~((uint32_t)Frs2s.sf));
}});
0x68: Trap::fandnot1({{fault = new IllegalInstruction;}});
0x69: Trap::fandnot1s({{fault = new IllegalInstruction;}});
@@ -637,7 +637,7 @@ decode OP default Unknown::unknown()
Frd.df = (double)(~((uint64_t)Frs1.df));
}});
0x6B: BasicOperate::fnot1s({{
- Frd.sf = (float)(~((uint32_t)Frs1.sf));
+ Frds.sf = (float)(~((uint32_t)Frs1s.sf));
}});
0x6C: Trap::fxor({{fault = new IllegalInstruction;}});
0x6D: Trap::fxors({{fault = new IllegalInstruction;}});
@@ -820,92 +820,248 @@ decode OP default Unknown::unknown()
}
0x3: decode OP3 {
format Load {
- 0x00: lduw({{Rd = Mem;}}, {{32}});
- 0x01: ldub({{Rd = Mem;}}, {{8}});
- 0x02: lduh({{Rd = Mem;}}, {{16}});
+ 0x00: lduw({{Rd = Mem.uw;}});
+ 0x01: ldub({{Rd = Mem.ub;}});
+ 0x02: lduh({{Rd = Mem.uhw;}});
0x03: ldd({{
- uint64_t val = Mem;
+ uint64_t val = Mem.udw;
RdLow = val<31:0>;
RdHigh = val<63:32>;
- }}, {{64}});
+ }});
}
format Store {
- 0x04: stw({{Mem = Rd.sw;}}, {{32}});
- 0x05: stb({{Mem = Rd.sb;}}, {{8}});
- 0x06: sth({{Mem = Rd.shw;}}, {{16}});
- 0x07: std({{Mem = RdLow<31:0> | (RdHigh<31:0> << 32);}}, {{64}});
+ 0x04: stw({{Mem.uw = Rd.sw;}});
+ 0x05: stb({{Mem.ub = Rd.sb;}});
+ 0x06: sth({{Mem.uhw = Rd.shw;}});
+ 0x07: std({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}});
}
format Load {
- 0x08: ldsw({{Rd = (int32_t)Mem;}}, {{32}});
- 0x09: ldsb({{Rd = (int8_t)Mem;}}, {{8}});
- 0x0A: ldsh({{Rd = (int16_t)Mem;}}, {{16}});
- 0x0B: ldx({{Rd = (int64_t)Mem;}}, {{64}});
+ 0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
+ 0x09: ldsb({{Rd = (int8_t)Mem.sb;}});
+ 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}});
+ 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}});
0x0D: ldstub({{
- Rd = Mem;
- Mem = 0xFF;
- }}, {{8}});
+ Rd = Mem.ub;
+ Mem.ub = 0xFF;
+ }});
}
- 0x0E: Store::stx({{Mem = Rd}}, {{64}});
- 0x0F: LoadStore::swap({{
- uint32_t temp = Rd;
- Rd = Mem;
- Mem = temp;
- }}, {{32}});
+ 0x0E: Store::stx({{Mem.udw = Rd}});
+ 0x0F: LoadStore::swap(
+ {{*temp = Rd.uw;
+ Rd.uw = Mem.uw;}},
+ {{Mem.uw = *temp;}});
format Load {
- 0x10: lduwa({{Rd = Mem;}}, {{32}});
- 0x11: lduba({{Rd = Mem;}}, {{8}});
- 0x12: lduha({{Rd = Mem;}}, {{16}});
+ 0x10: lduwa({{Rd = Mem.uw;}});
+ 0x11: lduba({{Rd = Mem.ub;}});
+ 0x12: lduha({{Rd = Mem.uhw;}});
0x13: ldda({{
- uint64_t val = Mem;
+ uint64_t val = Mem.udw;
RdLow = val<31:0>;
RdHigh = val<63:32>;
- }}, {{64}});
+ }});
}
format Store {
- 0x14: stwa({{Mem = Rd;}}, {{32}});
- 0x15: stba({{Mem = Rd;}}, {{8}});
- 0x16: stha({{Mem = Rd;}}, {{16}});
- 0x17: stda({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}});
+ 0x14: stwa({{Mem.uw = Rd;}});
+ 0x15: stba({{Mem.ub = Rd;}});
+ 0x16: stha({{Mem.uhw = Rd;}});
+ 0x17: stda({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}});
}
format Load {
- 0x18: ldswa({{Rd = (int32_t)Mem;}}, {{32}});
- 0x19: ldsba({{Rd = (int8_t)Mem;}}, {{8}});
- 0x1A: ldsha({{Rd = (int16_t)Mem;}}, {{16}});
- 0x1B: ldxa({{Rd = (int64_t)Mem;}}, {{64}});
+ 0x18: ldswa({{Rd = (int32_t)Mem.sw;}});
+ 0x19: ldsba({{Rd = (int8_t)Mem.sb;}});
+ 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}});
+ 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}});
}
- 0x1D: LoadStore::ldstuba({{
- Rd = Mem;
- Mem = 0xFF;
- }}, {{8}});
- 0x1E: Store::stxa({{Mem = Rd}}, {{64}});
- 0x1F: LoadStore::swapa({{
- uint32_t temp = Rd;
- Rd = Mem;
- Mem = temp;
- }}, {{32}});
+ 0x1D: LoadStore::ldstuba(
+ {{Rd = Mem.ub;}},
+ {{Mem.ub = 0xFF}});
+ 0x1E: Store::stxa({{Mem.udw = Rd}});
+ 0x1F: LoadStore::swapa(
+ {{*temp = Rd.uw;
+ Rd.uw = Mem.uw;}},
+ {{Mem.uw = *temp;}});
format Trap {
- 0x20: Load::ldf({{Frd.uw = Mem;}}, {{32}});
+ 0x20: Load::ldf({{Frd.uw = Mem.uw;}});
0x21: decode X {
- 0x0: Load::ldfsr({{Fsr = Mem<31:0> | Fsr<63:32>;}}, {{32}});
- 0x1: Load::ldxfsr({{Fsr = Mem;}}, {{64}});
+ 0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}});
+ 0x1: Load::ldxfsr({{Fsr = Mem.udw;}});
}
0x22: ldqf({{fault = new FpDisabled;}});
- 0x23: Load::lddf({{Frd.udw = Mem;}}, {{64}});
- 0x24: Store::stf({{Mem = Frd.uw;}}, {{32}});
+ 0x23: Load::lddf({{Frd.udw = Mem.udw;}});
+ 0x24: Store::stf({{Mem.uw = Frd.uw;}});
0x25: decode X {
- 0x0: Store::stfsr({{Mem = Fsr<31:0>;}}, {{32}});
- 0x1: Store::stxfsr({{Mem = Fsr;}}, {{64}});
+ 0x0: Store::stfsr({{Mem.uw = Fsr<31:0>;}});
+ 0x1: Store::stxfsr({{Mem.udw = Fsr;}});
}
0x26: stqf({{fault = new FpDisabled;}});
- 0x27: Store::stdf({{Mem = Frd.udw;}}, {{64}});
+ 0x27: Store::stdf({{Mem.udw = Frd.udw;}});
0x2D: Nop::prefetch({{ }});
- 0x30: Load::ldfa({{Frd.uw = Mem;}}, {{32}});
+ 0x30: Load::ldfa({{Frd.uw = Mem.uw;}});
0x32: ldqfa({{fault = new FpDisabled;}});
- 0x33: Load::lddfa({{Frd.udw = Mem;}}, {{64}});
- 0x34: Store::stfa({{Mem = Frd.uw;}}, {{32}});
+ format LoadAlt {
+ 0x33: decode EXT_ASI {
+ //ASI_NUCLEUS
+ 0x04: FailUnimpl::lddfa_n();
+ //ASI_NUCLEUS_LITTLE
+ 0x0C: FailUnimpl::lddfa_nl();
+ //ASI_AS_IF_USER_PRIMARY
+ 0x10: FailUnimpl::lddfa_aiup();
+ //ASI_AS_IF_USER_PRIMARY_LITTLE
+ 0x18: FailUnimpl::lddfa_aiupl();
+ //ASI_AS_IF_USER_SECONDARY
+ 0x11: FailUnimpl::lddfa_aius();
+ //ASI_AS_IF_USER_SECONDARY_LITTLE
+ 0x19: FailUnimpl::lddfa_aiusl();
+ //ASI_REAL
+ 0x14: FailUnimpl::lddfa_real();
+ //ASI_REAL_LITTLE
+ 0x1C: FailUnimpl::lddfa_real_l();
+ //ASI_REAL_IO
+ 0x15: FailUnimpl::lddfa_real_io();
+ //ASI_REAL_IO_LITTLE
+ 0x1D: FailUnimpl::lddfa_real_io_l();
+ //ASI_PRIMARY
+ 0x80: FailUnimpl::lddfa_p();
+ //ASI_PRIMARY_LITTLE
+ 0x88: FailUnimpl::lddfa_pl();
+ //ASI_SECONDARY
+ 0x81: FailUnimpl::lddfa_s();
+ //ASI_SECONDARY_LITTLE
+ 0x89: FailUnimpl::lddfa_sl();
+ //ASI_PRIMARY_NO_FAULT
+ 0x82: FailUnimpl::lddfa_pnf();
+ //ASI_PRIMARY_NO_FAULT_LITTLE
+ 0x8A: FailUnimpl::lddfa_pnfl();
+ //ASI_SECONDARY_NO_FAULT
+ 0x83: FailUnimpl::lddfa_snf();
+ //ASI_SECONDARY_NO_FAULT_LITTLE
+ 0x8B: FailUnimpl::lddfa_snfl();
+
+ format BlockLoad {
+ // LDBLOCKF
+ //ASI_BLOCK_AS_IF_USER_PRIMARY
+ 0x16: FailUnimpl::ldblockf_aiup();
+ //ASI_BLOCK_AS_IF_USER_SECONDARY
+ 0x17: FailUnimpl::ldblockf_aius();
+ //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
+ 0x1E: FailUnimpl::ldblockf_aiupl();
+ //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
+ 0x1F: FailUnimpl::ldblockf_aiusl();
+ //ASI_BLOCK_PRIMARY
+ 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}});
+ //ASI_BLOCK_SECONDARY
+ 0xF1: FailUnimpl::ldblockf_s();
+ //ASI_BLOCK_PRIMARY_LITTLE
+ 0xF8: FailUnimpl::ldblockf_pl();
+ //ASI_BLOCK_SECONDARY_LITTLE
+ 0xF9: FailUnimpl::ldblockf_sl();
+ }
+
+ //LDSHORTF
+ //ASI_FL8_PRIMARY
+ 0xD0: FailUnimpl::ldshortf_8p();
+ //ASI_FL8_SECONDARY
+ 0xD1: FailUnimpl::ldshortf_8s();
+ //ASI_FL8_PRIMARY_LITTLE
+ 0xD8: FailUnimpl::ldshortf_8pl();
+ //ASI_FL8_SECONDARY_LITTLE
+ 0xD9: FailUnimpl::ldshortf_8sl();
+ //ASI_FL16_PRIMARY
+ 0xD2: FailUnimpl::ldshortf_16p();
+ //ASI_FL16_SECONDARY
+ 0xD3: FailUnimpl::ldshortf_16s();
+ //ASI_FL16_PRIMARY_LITTLE
+ 0xDA: FailUnimpl::ldshortf_16pl();
+ //ASI_FL16_SECONDARY_LITTLE
+ 0xDB: FailUnimpl::ldshortf_16sl();
+ //Not an ASI which is legal with lddfa
+ default: Trap::lddfa_bad_asi(
+ {{fault = new DataAccessException;}});
+ }
+ }
+ 0x34: Store::stfa({{Mem.uw = Frd.uw;}});
0x36: stqfa({{fault = new FpDisabled;}});
- //XXX need to work in the ASI thing
- 0x37: Store::stdfa({{Mem = Frd.udw;}}, {{64}});
+ format StoreAlt {
+ 0x37: decode EXT_ASI {
+ //ASI_NUCLEUS
+ 0x04: FailUnimpl::stdfa_n();
+ //ASI_NUCLEUS_LITTLE
+ 0x0C: FailUnimpl::stdfa_nl();
+ //ASI_AS_IF_USER_PRIMARY
+ 0x10: FailUnimpl::stdfa_aiup();
+ //ASI_AS_IF_USER_PRIMARY_LITTLE
+ 0x18: FailUnimpl::stdfa_aiupl();
+ //ASI_AS_IF_USER_SECONDARY
+ 0x11: FailUnimpl::stdfa_aius();
+ //ASI_AS_IF_USER_SECONDARY_LITTLE
+ 0x19: FailUnimpl::stdfa_aiusl();
+ //ASI_REAL
+ 0x14: FailUnimpl::stdfa_real();
+ //ASI_REAL_LITTLE
+ 0x1C: FailUnimpl::stdfa_real_l();
+ //ASI_REAL_IO
+ 0x15: FailUnimpl::stdfa_real_io();
+ //ASI_REAL_IO_LITTLE
+ 0x1D: FailUnimpl::stdfa_real_io_l();
+ //ASI_PRIMARY
+ 0x80: FailUnimpl::stdfa_p();
+ //ASI_PRIMARY_LITTLE
+ 0x88: FailUnimpl::stdfa_pl();
+ //ASI_SECONDARY
+ 0x81: FailUnimpl::stdfa_s();
+ //ASI_SECONDARY_LITTLE
+ 0x89: FailUnimpl::stdfa_sl();
+ //ASI_PRIMARY_NO_FAULT
+ 0x82: FailUnimpl::stdfa_pnf();
+ //ASI_PRIMARY_NO_FAULT_LITTLE
+ 0x8A: FailUnimpl::stdfa_pnfl();
+ //ASI_SECONDARY_NO_FAULT
+ 0x83: FailUnimpl::stdfa_snf();
+ //ASI_SECONDARY_NO_FAULT_LITTLE
+ 0x8B: FailUnimpl::stdfa_snfl();
+
+ format BlockStore {
+ // STBLOCKF
+ //ASI_BLOCK_AS_IF_USER_PRIMARY
+ 0x16: FailUnimpl::stblockf_aiup();
+ //ASI_BLOCK_AS_IF_USER_SECONDARY
+ 0x17: FailUnimpl::stblockf_aius();
+ //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
+ 0x1E: FailUnimpl::stblockf_aiupl();
+ //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
+ 0x1F: FailUnimpl::stblockf_aiusl();
+ //ASI_BLOCK_PRIMARY
+ 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}});
+ //ASI_BLOCK_SECONDARY
+ 0xF1: FailUnimpl::stblockf_s();
+ //ASI_BLOCK_PRIMARY_LITTLE
+ 0xF8: FailUnimpl::stblockf_pl();
+ //ASI_BLOCK_SECONDARY_LITTLE
+ 0xF9: FailUnimpl::stblockf_sl();
+ }
+
+ //STSHORTF
+ //ASI_FL8_PRIMARY
+ 0xD0: FailUnimpl::stshortf_8p();
+ //ASI_FL8_SECONDARY
+ 0xD1: FailUnimpl::stshortf_8s();
+ //ASI_FL8_PRIMARY_LITTLE
+ 0xD8: FailUnimpl::stshortf_8pl();
+ //ASI_FL8_SECONDARY_LITTLE
+ 0xD9: FailUnimpl::stshortf_8sl();
+ //ASI_FL16_PRIMARY
+ 0xD2: FailUnimpl::stshortf_16p();
+ //ASI_FL16_SECONDARY
+ 0xD3: FailUnimpl::stshortf_16s();
+ //ASI_FL16_PRIMARY_LITTLE
+ 0xDA: FailUnimpl::stshortf_16pl();
+ //ASI_FL16_SECONDARY_LITTLE
+ 0xDB: FailUnimpl::stshortf_16sl();
+ //Not an ASI which is legal with lddfa
+ default: Trap::stdfa_bad_asi(
+ {{fault = new DataAccessException;}});
+ }
+ }
0x3C: Cas::casa({{
uint64_t val = Mem.uw;
if(Rs2.uw == val)
diff --git a/src/arch/sparc/isa/formats.isa b/src/arch/sparc/isa/formats.isa
deleted file mode 100644
index 17d68061b..000000000
--- a/src/arch/sparc/isa/formats.isa
+++ /dev/null
@@ -1,28 +0,0 @@
-//Include the basic format
-//Templates from this format are used later
-##include "formats/basic.isa"
-
-//Include the noop format
-##include "formats/nop.isa"
-
-//Include the integerOp and integerOpCc format
-##include "formats/integerop.isa"
-
-//Include the memory format
-##include "formats/mem.isa"
-
-//Include the compare and swap format
-##include "formats/cas.isa"
-
-//Include the trap format
-##include "formats/trap.isa"
-
-//Include the "unknown" format
-##include "formats/unknown.isa"
-
-//Include the priveleged mode format
-##include "formats/priv.isa"
-
-//Include the branch format
-##include "formats/branch.isa"
-
diff --git a/src/arch/sparc/isa/formats/basic.isa b/src/arch/sparc/isa/formats/basic.isa
index 0a47a7ffe..a4c05387b 100644
--- a/src/arch/sparc/isa/formats/basic.isa
+++ b/src/arch/sparc/isa/formats/basic.isa
@@ -33,6 +33,14 @@ def template BasicExecDeclare {{
Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
}};
+// Definitions of execute methods that panic.
+def template BasicExecPanic {{
+ Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
+ {
+ panic("Execute method called when it shouldn't!");
+ }
+}};
+
// Basic instruction class declaration template.
def template BasicDeclare {{
/**
@@ -42,14 +50,14 @@ def template BasicDeclare {{
{
public:
// Constructor.
- %(class_name)s(MachInst machInst);
+ %(class_name)s(ExtMachInst machInst);
%(BasicExecDeclare)s
};
}};
// Basic instruction class constructor template.
def template BasicConstructor {{
- inline %(class_name)s::%(class_name)s(MachInst machInst)
+ inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
{
%(constructor)s;
@@ -80,6 +88,11 @@ def template BasicDecode {{
return new %(class_name)s(machInst);
}};
+// Basic decode template, passing mnemonic in as string arg to constructor.
+def template BasicDecodeWithMnemonic {{
+ return new %(class_name)s("%(mnemonic)s", machInst);
+}};
+
// The most basic instruction format... used only for a few misc. insts
def format BasicOperate(code, *flags) {{
iop = InstObjParams(name, Name, 'SparcStaticInst',
diff --git a/src/arch/sparc/isa/formats/branch.isa b/src/arch/sparc/isa/formats/branch.isa
index 2c206354b..5fb7ade2d 100644
--- a/src/arch/sparc/isa/formats/branch.isa
+++ b/src/arch/sparc/isa/formats/branch.isa
@@ -80,7 +80,7 @@ output header {{
OpClass __opClass) :
BranchDisp(mnem, _machInst, __opClass)
{
- disp = sign_ext(_machInst << 2, bits + 2);
+ disp = sext<bits + 2>((_machInst & mask(bits)) << 2);
}
};
@@ -95,7 +95,7 @@ output header {{
OpClass __opClass) :
BranchDisp(mnem, _machInst, __opClass)
{
- disp = sign_ext((D16HI << 16) | (D16LO << 2), 18);
+ disp = sext<18>((D16HI << 16) | (D16LO << 2));
}
};
@@ -108,7 +108,7 @@ output header {{
protected:
// Constructor
BranchImm13(const char *mnem, MachInst _machInst, OpClass __opClass) :
- Branch(mnem, _machInst, __opClass), imm(sign_ext(SIMM13, 13))
+ Branch(mnem, _machInst, __opClass), imm(sext<13>(SIMM13))
{
}
diff --git a/src/arch/sparc/isa/formats/formats.isa b/src/arch/sparc/isa/formats/formats.isa
new file mode 100644
index 000000000..5b81a1ab1
--- /dev/null
+++ b/src/arch/sparc/isa/formats/formats.isa
@@ -0,0 +1,62 @@
+// Copyright (c) 2006 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Gabe Black
+
+//Include the basic format
+//Templates from this format are used later
+##include "basic.isa"
+
+//Include base classes for microcoding instructions
+##include "micro.isa"
+
+//Include the noop format
+##include "nop.isa"
+
+//Include the integerOp and integerOpCc format
+##include "integerop.isa"
+
+//Include the memory formats
+##include "mem/mem.isa"
+
+//Include the compare and swap format
+##include "cas.isa"
+
+//Include the trap format
+##include "trap.isa"
+
+//Include the unimplemented format
+##include "unimp.isa"
+
+//Include the "unknown" format
+##include "unknown.isa"
+
+//Include the priveleged mode format
+##include "priv.isa"
+
+//Include the branch format
+##include "branch.isa"
+
diff --git a/src/arch/sparc/isa/formats/integerop.isa b/src/arch/sparc/isa/formats/integerop.isa
index 83c7e6958..4f8ebebcc 100644
--- a/src/arch/sparc/isa/formats/integerop.isa
+++ b/src/arch/sparc/isa/formats/integerop.isa
@@ -87,7 +87,7 @@ output header {{
OpClass __opClass) :
IntOpImm(mnem, _machInst, __opClass)
{
- imm = sign_ext(SIMM10, 10);
+ imm = sext<10>(SIMM10);
}
};
@@ -102,7 +102,7 @@ output header {{
OpClass __opClass) :
IntOpImm(mnem, _machInst, __opClass)
{
- imm = sign_ext(SIMM11, 11);
+ imm = sext<11>(SIMM11);
}
};
@@ -117,7 +117,7 @@ output header {{
OpClass __opClass) :
IntOpImm(mnem, _machInst, __opClass)
{
- imm = sign_ext(SIMM13, 13);
+ imm = sext<13>(SIMM13);
}
};
@@ -264,13 +264,13 @@ let {{
(usesImm, code, immCode,
rString, iString) = splitOutImm(code)
iop = InstObjParams(name, Name, 'IntOp', code,
- opt_flags, ("cc_code", ccCode))
+ opt_flags, {"cc_code": ccCode})
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
exec_output = IntOpExecute.subst(iop)
if usesImm:
imm_iop = InstObjParams(name, Name + 'Imm', 'IntOpImm' + iString,
- immCode, opt_flags, ("cc_code", ccCode))
+ immCode, opt_flags, {"cc_code": ccCode})
header_output += BasicDeclare.subst(imm_iop)
decoder_output += BasicConstructor.subst(imm_iop)
exec_output += IntOpExecute.subst(imm_iop)
@@ -341,7 +341,7 @@ def format IntOpCcRes(code, *opt_flags) {{
def format SetHi(code, *opt_flags) {{
iop = InstObjParams(name, Name, 'SetHi',
- code, opt_flags, ("cc_code", ''))
+ code, opt_flags, {"cc_code": ''})
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
exec_output = IntOpExecute.subst(iop)
diff --git a/src/arch/sparc/isa/formats/mem.isa b/src/arch/sparc/isa/formats/mem/basicmem.isa
index 9011c1fc6..c13194d0f 100644
--- a/src/arch/sparc/isa/formats/mem.isa
+++ b/src/arch/sparc/isa/formats/mem/basicmem.isa
@@ -1,3 +1,32 @@
+// Copyright (c) 2006 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Ali Saidi
+// Gabe Black
+
////////////////////////////////////////////////////////////////////
//
// Mem instructions
@@ -30,15 +59,13 @@ output header {{
// Constructor
MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
- Mem(mnem, _machInst, __opClass)
- {
- imm = sign_ext(SIMM13, 13);
- }
+ Mem(mnem, _machInst, __opClass), imm(sext<13>(SIMM13))
+ {}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
- int32_t imm;
+ const int32_t imm;
};
}};
@@ -99,73 +126,69 @@ output decoder {{
}
}};
-def template MemExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
- Trace::InstRecord *traceData) const
+def template MemDeclare {{
+ /**
+ * Static instruction class for "%(mnemonic)s".
+ */
+ class %(class_name)s : public %(base_class)s
{
- Fault fault = NoFault;
- Addr EA;
- %(op_decl)s;
- %(op_rd)s;
- %(ea_code)s;
- DPRINTF(Sparc, "The address is 0x%x\n", EA);
- %(load)s;
- %(code)s;
-
- if(fault == NoFault)
- {
- %(store)s;
- //Write the resulting state to the execution context
- %(op_wb)s;
- }
+ public:
- return fault;
- }
+ /// Constructor.
+ %(class_name)s(ExtMachInst machInst);
+
+ %(BasicExecDeclare)s
+
+ %(InitiateAccDeclare)s
+
+ %(CompleteAccDeclare)s
+ };
}};
let {{
- # Leave memAccessFlags at 0 for now
- loadString = "xc->read(EA, (uint%(width)s_t&)Mem, 0);"
- storeString = "uint64_t write_result = 0; \
- xc->write((uint%(width)s_t)Mem, EA, 0, &write_result);"
-
- def doMemFormat(code, load, store, name, Name, opt_flags):
+ def doMemFormat(code, execute, faultCode, name, Name, opt_flags):
addrCalcReg = 'EA = Rs1 + Rs2;'
addrCalcImm = 'EA = Rs1 + imm;'
iop = InstObjParams(name, Name, 'Mem', code,
- opt_flags, ("ea_code", addrCalcReg),
- ("load", load), ("store", store))
- iop_imm = InstObjParams(name, Name + 'Imm', 'MemImm', code,
- opt_flags, ("ea_code", addrCalcImm),
- ("load", load), ("store", store))
- header_output = BasicDeclare.subst(iop) + BasicDeclare.subst(iop_imm)
+ opt_flags, {"fault_check": faultCode, "ea_code": addrCalcReg})
+ iop_imm = InstObjParams(name, Name + "Imm", 'MemImm', code,
+ opt_flags, {"fault_check": faultCode, "ea_code": addrCalcImm})
+ header_output = MemDeclare.subst(iop) + MemDeclare.subst(iop_imm)
decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm)
decode_block = ROrImmDecode.subst(iop)
- exec_output = MemExecute.subst(iop) + MemExecute.subst(iop_imm)
+ exec_output = doSplitExecute(code, addrCalcReg, addrCalcImm, execute,
+ faultCode, name, name + "Imm", Name, Name + "Imm", opt_flags)
return (header_output, decoder_output, exec_output, decode_block)
}};
-def format Load(code, width, *opt_flags) {{
+def format LoadAlt(code, *opt_flags) {{
(header_output,
decoder_output,
exec_output,
- decode_block) = doMemFormat(code,
- loadString % {"width":width}, '', name, Name, opt_flags)
+ decode_block) = doMemFormat(code, LoadExecute,
+ AlternateAsiPrivFaultCheck, name, Name, opt_flags)
}};
-def format Store(code, width, *opt_flags) {{
+def format StoreAlt(code, *opt_flags) {{
(header_output,
decoder_output,
exec_output,
- decode_block) = doMemFormat(code, '',
- storeString % {"width":width}, name, Name, opt_flags)
+ decode_block) = doMemFormat(code, StoreExecute,
+ AlternateAsiPrivFaultCheck, name, Name, opt_flags)
+}};
+
+def format Load(code, *opt_flags) {{
+ (header_output,
+ decoder_output,
+ exec_output,
+ decode_block) = doMemFormat(code,
+ LoadExecute, '', name, Name, opt_flags)
}};
-def format LoadStore(code, width, *opt_flags) {{
+def format Store(code, *opt_flags) {{
(header_output,
decoder_output,
exec_output,
decode_block) = doMemFormat(code,
- loadString % {"width":width}, storeString % {"width":width},
- name, Name, opt_flags)
+ StoreExecute, '', name, Name, opt_flags)
}};
diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa
new file mode 100644
index 000000000..93ad1b2b8
--- /dev/null
+++ b/src/arch/sparc/isa/formats/mem/blockmem.isa
@@ -0,0 +1,337 @@
+// Copyright (c) 2006 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Ali Saidi
+// Gabe Black
+
+////////////////////////////////////////////////////////////////////
+//
+// Block Memory instructions
+//
+
+output header {{
+
+ class BlockMem : public SparcMacroInst
+ {
+ protected:
+
+ // Constructor
+ // We make the assumption that all block memory operations
+ // Will take 8 instructions to execute
+ BlockMem(const char *mnem, ExtMachInst _machInst) :
+ SparcMacroInst(mnem, _machInst, No_OpClass, 8)
+ {}
+ };
+
+ class BlockMemImm : public BlockMem
+ {
+ protected:
+
+ // Constructor
+ BlockMemImm(const char *mnem, ExtMachInst _machInst) :
+ BlockMem(mnem, _machInst)
+ {}
+ };
+
+ class BlockMemMicro : public SparcDelayedMicroInst
+ {
+ protected:
+
+ // Constructor
+ BlockMemMicro(const char *mnem, ExtMachInst _machInst,
+ OpClass __opClass, int8_t _offset) :
+ SparcDelayedMicroInst(mnem, _machInst, __opClass),
+ offset(_offset)
+ {}
+
+ std::string generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const;
+
+ const int8_t offset;
+ };
+
+ class BlockMemImmMicro : public BlockMemMicro
+ {
+ protected:
+
+ // Constructor
+ BlockMemImmMicro(const char *mnem, ExtMachInst _machInst,
+ OpClass __opClass, int8_t _offset) :
+ BlockMemMicro(mnem, _machInst, __opClass, _offset),
+ imm(sext<13>(SIMM13))
+ {}
+
+ std::string generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const;
+
+ const int32_t imm;
+ };
+}};
+
+output decoder {{
+ std::string BlockMemMicro::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
+ {
+ std::stringstream response;
+ bool load = flags[IsLoad];
+ bool save = flags[IsStore];
+
+ printMnemonic(response, mnemonic);
+ if(save)
+ {
+ printReg(response, _srcRegIdx[0]);
+ ccprintf(response, ", ");
+ }
+ ccprintf(response, "[ ");
+ printReg(response, _srcRegIdx[!save ? 0 : 1]);
+ ccprintf(response, " + ");
+ printReg(response, _srcRegIdx[!save ? 1 : 2]);
+ ccprintf(response, " ]");
+ if(load)
+ {
+ ccprintf(response, ", ");
+ printReg(response, _destRegIdx[0]);
+ }
+
+ return response.str();
+ }
+
+ std::string BlockMemImmMicro::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
+ {
+ std::stringstream response;
+ bool load = flags[IsLoad];
+ bool save = flags[IsStore];
+
+ printMnemonic(response, mnemonic);
+ if(save)
+ {
+ printReg(response, _srcRegIdx[1]);
+ ccprintf(response, ", ");
+ }
+ ccprintf(response, "[ ");
+ printReg(response, _srcRegIdx[0]);
+ if(imm >= 0)
+ ccprintf(response, " + 0x%x ]", imm);
+ else
+ ccprintf(response, " + -0x%x ]", -imm);
+ if(load)
+ {
+ ccprintf(response, ", ");
+ printReg(response, _destRegIdx[0]);
+ }
+
+ return response.str();
+ }
+
+}};
+
+def template BlockMemDeclare {{
+ /**
+ * Static instruction class for a block memory operation
+ */
+ class %(class_name)s : public %(base_class)s
+ {
+ public:
+ //Constructor
+ %(class_name)s(ExtMachInst machInst);
+
+ protected:
+ class %(class_name)s_0 : public %(base_class)sMicro
+ {
+ public:
+ //Constructor
+ %(class_name)s_0(ExtMachInst machInst);
+ %(BasicExecDeclare)s
+ %(InitiateAccDeclare)s
+ %(CompleteAccDeclare)s
+ };
+
+ class %(class_name)s_1 : public %(base_class)sMicro
+ {
+ public:
+ //Constructor
+ %(class_name)s_1(ExtMachInst machInst);
+ %(BasicExecDeclare)s
+ %(InitiateAccDeclare)s
+ %(CompleteAccDeclare)s
+ };
+
+ class %(class_name)s_2 : public %(base_class)sMicro
+ {
+ public:
+ //Constructor
+ %(class_name)s_2(ExtMachInst machInst);
+ %(BasicExecDeclare)s
+ %(InitiateAccDeclare)s
+ %(CompleteAccDeclare)s
+ };
+
+ class %(class_name)s_3 : public %(base_class)sMicro
+ {
+ public:
+ //Constructor
+ %(class_name)s_3(ExtMachInst machInst);
+ %(BasicExecDeclare)s
+ %(InitiateAccDeclare)s
+ %(CompleteAccDeclare)s
+ };
+
+ class %(class_name)s_4 : public %(base_class)sMicro
+ {
+ public:
+ //Constructor
+ %(class_name)s_4(ExtMachInst machInst);
+ %(BasicExecDeclare)s
+ %(InitiateAccDeclare)s
+ %(CompleteAccDeclare)s
+ };
+
+ class %(class_name)s_5 : public %(base_class)sMicro
+ {
+ public:
+ //Constructor
+ %(class_name)s_5(ExtMachInst machInst);
+ %(BasicExecDeclare)s
+ %(InitiateAccDeclare)s
+ %(CompleteAccDeclare)s
+ };
+
+ class %(class_name)s_6 : public %(base_class)sMicro
+ {
+ public:
+ //Constructor
+ %(class_name)s_6(ExtMachInst machInst);
+ %(BasicExecDeclare)s
+ %(InitiateAccDeclare)s
+ %(CompleteAccDeclare)s
+ };
+
+ class %(class_name)s_7 : public %(base_class)sMicro
+ {
+ public:
+ //Constructor
+ %(class_name)s_7(ExtMachInst machInst);
+ %(BasicExecDeclare)s
+ %(InitiateAccDeclare)s
+ %(CompleteAccDeclare)s
+ };
+ };
+}};
+
+// Basic instruction class constructor template.
+def template BlockMemConstructor {{
+ inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
+ : %(base_class)s("%(mnemonic)s", machInst)
+ {
+ %(constructor)s;
+ microOps[0] = new %(class_name)s_0(machInst);
+ microOps[1] = new %(class_name)s_1(machInst);
+ microOps[2] = new %(class_name)s_2(machInst);
+ microOps[3] = new %(class_name)s_3(machInst);
+ microOps[4] = new %(class_name)s_4(machInst);
+ microOps[5] = new %(class_name)s_5(machInst);
+ microOps[6] = new %(class_name)s_6(machInst);
+ microOps[7] = new %(class_name)s_7(machInst);
+ }
+}};
+
+def template BlockMemMicroConstructor {{
+ inline %(class_name)s::
+ %(class_name)s_%(micro_pc)s::
+ %(class_name)s_%(micro_pc)s(ExtMachInst machInst) :
+ %(base_class)sMicro("%(mnemonic)s[%(micro_pc)s]",
+ machInst, %(op_class)s, %(micro_pc)s * 8)
+ {
+ %(constructor)s;
+ %(set_flags)s;
+ }
+}};
+
+let {{
+
+ def doBlockMemFormat(code, faultCode, execute, name, Name, opt_flags):
+ # XXX Need to take care of pstate.hpriv as well. The lower ASIs
+ # are split into ones that are available in priv and hpriv, and
+ # those that are only available in hpriv
+ addrCalcReg = 'EA = Rs1 + Rs2 + offset;'
+ addrCalcImm = 'EA = Rs1 + imm + offset;'
+ iop = InstObjParams(name, Name, 'BlockMem', code, opt_flags)
+ iop_imm = InstObjParams(name, Name + 'Imm', 'BlockMemImm', code, opt_flags)
+ header_output = BlockMemDeclare.subst(iop) + BlockMemDeclare.subst(iop_imm)
+ decoder_output = BlockMemConstructor.subst(iop) + BlockMemConstructor.subst(iop_imm)
+ decode_block = ROrImmDecode.subst(iop)
+ matcher = re.compile(r'Frd_N')
+ exec_output = ''
+ for microPc in range(8):
+ flag_code = ''
+ if (microPc == 7):
+ flag_code = "flags[IsLastMicroOp] = true;"
+ pcedCode = matcher.sub("Frd_%d" % microPc, code)
+ iop = InstObjParams(name, Name, 'BlockMem', pcedCode,
+ opt_flags, {"ea_code": addrCalcReg,
+ "fault_check": faultCode, "micro_pc": microPc,
+ "set_flags": flag_code})
+ iop_imm = InstObjParams(name, Name + 'Imm', 'BlockMemImm', pcedCode,
+ opt_flags, {"ea_code": addrCalcImm,
+ "fault_check": faultCode, "micro_pc": microPc,
+ "set_flags": flag_code})
+ decoder_output += BlockMemMicroConstructor.subst(iop)
+ decoder_output += BlockMemMicroConstructor.subst(iop_imm)
+ exec_output += doSplitExecute(
+ pcedCode, addrCalcReg, addrCalcImm, execute, faultCode,
+ makeMicroName(name, microPc),
+ makeMicroName(name + "Imm", microPc),
+ makeMicroName(Name, microPc),
+ makeMicroName(Name + "Imm", microPc),
+ opt_flags);
+ faultCode = ''
+ return (header_output, decoder_output, exec_output, decode_block)
+}};
+
+def format BlockLoad(code, *opt_flags) {{
+ # We need to make sure to check the highest priority fault last.
+ # That way, if other faults have been detected, they'll be overwritten
+ # rather than the other way around.
+ faultCode = AlternateASIPrivFaultCheck + BlockAlignmentFaultCheck
+ (header_output,
+ decoder_output,
+ exec_output,
+ decode_block) = doBlockMemFormat(code, faultCode,
+ LoadExecute, name, Name, opt_flags)
+}};
+
+def format BlockStore(code, *opt_flags) {{
+ # We need to make sure to check the highest priority fault last.
+ # That way, if other faults have been detected, they'll be overwritten
+ # rather than the other way around.
+ faultCode = AlternateASIPrivFaultCheck + BlockAlignmentFaultCheck
+ (header_output,
+ decoder_output,
+ exec_output,
+ decode_block) = doBlockMemFormat(code, faultCode,
+ StoreExecute, name, Name, opt_flags)
+}};
diff --git a/src/arch/sparc/isa/formats/mem/mem.isa b/src/arch/sparc/isa/formats/mem/mem.isa
new file mode 100644
index 000000000..20a22c45d
--- /dev/null
+++ b/src/arch/sparc/isa/formats/mem/mem.isa
@@ -0,0 +1,45 @@
+// Copyright (c) 2006 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Ali Saidi
+// Gabe Black
+
+////////////////////////////////////////////////////////////////////
+//
+// Mem formats
+//
+
+//Include mem utility templates and functions
+##include "util.isa"
+
+//Include the basic memory format
+##include "basicmem.isa"
+
+//Include the block memory format
+##include "blockmem.isa"
+
+//Include the load/store memory format
+##include "loadstore.isa"
diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa
new file mode 100644
index 000000000..241a25d17
--- /dev/null
+++ b/src/arch/sparc/isa/formats/mem/util.isa
@@ -0,0 +1,226 @@
+// Copyright (c) 2006 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Ali Saidi
+// Gabe Black
+// Steve Reinhardt
+
+////////////////////////////////////////////////////////////////////
+//
+// Mem utility templates and functions
+//
+
+//This template provides the execute functions for a load
+def template LoadExecute {{
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData) const
+ {
+ Fault fault = NoFault;
+ Addr EA;
+ %(op_decl)s;
+ %(op_rd)s;
+ %(ea_code)s;
+ DPRINTF(Sparc, "The address is 0x%x\n", EA);
+ %(fault_check)s;
+ if(fault == NoFault)
+ {
+ fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, 0);
+ }
+ if(fault == NoFault)
+ {
+ %(code)s;
+ }
+ if(fault == NoFault)
+ {
+ //Write the resulting state to the execution context
+ %(op_wb)s;
+ }
+
+ return fault;
+ }
+
+ Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
+ Trace::InstRecord * traceData) const
+ {
+ Fault fault = NoFault;
+ Addr EA;
+ uint%(mem_acc_size)s_t Mem;
+ %(ea_decl)s;
+ %(ea_rd)s;
+ %(ea_code)s;
+ %(fault_check)s;
+ if(fault == NoFault)
+ {
+ fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, 0);
+ }
+ return fault;
+ }
+
+ Fault %(class_name)s::completeAcc(PacketPtr pkt, %(CPU_exec_context)s * xc,
+ Trace::InstRecord * traceData) const
+ {
+ Fault fault = NoFault;
+ %(code_decl)s;
+ %(code_rd)s;
+ Mem = pkt->get<typeof(Mem)>();
+ %(code)s;
+ if(fault == NoFault)
+ {
+ %(code_wb)s;
+ }
+ return fault;
+ }
+}};
+
+//This template provides the execute functions for a store
+def template StoreExecute {{
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData) const
+ {
+ Fault fault = NoFault;
+ uint64_t write_result = 0;
+ Addr EA;
+ %(op_decl)s;
+ %(op_rd)s;
+ %(ea_code)s;
+ DPRINTF(Sparc, "The address is 0x%x\n", EA);
+ %(fault_check)s;
+ if(fault == NoFault)
+ {
+ %(code)s;
+ }
+ if(fault == NoFault)
+ {
+ fault = xc->write((uint%(mem_acc_size)s_t)Mem, EA, 0, &write_result);
+ }
+ if(fault == NoFault)
+ {
+ //Write the resulting state to the execution context
+ %(op_wb)s;
+ }
+
+ return fault;
+ }
+
+ Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
+ Trace::InstRecord * traceData) const
+ {
+ Fault fault = NoFault;
+ uint64_t write_result = 0;
+ Addr EA;
+ %(op_decl)s;
+ %(op_rd)s;
+ %(ea_code)s;
+ DPRINTF(Sparc, "The address is 0x%x\n", EA);
+ %(fault_check)s;
+ if(fault == NoFault)
+ {
+ %(code)s;
+ }
+ if(fault == NoFault)
+ {
+ fault = xc->write((uint%(mem_acc_size)s_t)Mem, EA, 0, &write_result);
+ }
+ if(fault == NoFault)
+ {
+ //Write the resulting state to the execution context
+ %(op_wb)s;
+ }
+ return fault;
+ }
+
+ Fault %(class_name)s::completeAcc(PacketPtr, %(CPU_exec_context)s * xc,
+ Trace::InstRecord * traceData) const
+ {
+ return NoFault;
+ }
+}};
+
+//This delcares the initiateAcc function in memory operations
+def template InitiateAccDeclare {{
+ Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
+}};
+
+//This declares the completeAcc function in memory operations
+def template CompleteAccDeclare {{
+ Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
+}};
+
+//Here are some code snippets which check for various fault conditions
+let {{
+ # The LSB can be zero, since it's really the MSB in doubles and quads
+ # and we're dealing with doubles
+ BlockAlignmentFaultCheck = '''
+ if(RD & 0xe)
+ fault = new IllegalInstruction;
+ else if(EA & 0x3f)
+ fault = new MemAddressNotAligned;
+ '''
+ # XXX Need to take care of pstate.hpriv as well. The lower ASIs
+ # are split into ones that are available in priv and hpriv, and
+ # those that are only available in hpriv
+ AlternateASIPrivFaultCheck = '''
+ if(bits(Pstate,2,2) == 0 && (EXT_ASI & 0x80) == 0)
+ fault = new PrivilegedAction;
+ else if(AsiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2))
+ fault = new PrivilegedAction;
+ '''
+
+}};
+
+//A simple function to generate the name of the macro op of a certain
+//instruction at a certain micropc
+let {{
+ def makeMicroName(name, microPc):
+ return name + "::" + name + "_" + str(microPc)
+}};
+
+//This function properly generates the execute functions for one of the
+//templates above. This is needed because in one case, ea computation,
+//fault checks and the actual code all occur in the same function,
+//and in the other they're distributed across two. Also note that for
+//execute functions, the name of the base class doesn't matter.
+let {{
+ def doSplitExecute(code, eaRegCode, eaImmCode, execute,
+ faultCode, nameReg, nameImm, NameReg, NameImm, opt_flags):
+ codeIop = InstObjParams(nameReg, NameReg, '', code, opt_flags)
+ executeCode = ''
+ for (eaCode, name, Name) in (
+ (eaRegCode, nameReg, NameReg),
+ (eaImmCode, nameImm, NameImm)):
+ eaIop = InstObjParams(name, Name, '', eaCode,
+ opt_flags, {"fault_check": faultCode})
+ iop = InstObjParams(name, Name, '', code, opt_flags,
+ {"fault_check": faultCode, "ea_code" : eaCode})
+ (iop.ea_decl,
+ iop.ea_rd,
+ iop.ea_wb) = (eaIop.op_decl, eaIop.op_rd, eaIop.op_wb)
+ (iop.code_decl,
+ iop.code_rd,
+ iop.code_wb) = (codeIop.op_decl, codeIop.op_rd, codeIop.op_wb)
+ executeCode += execute.subst(iop)
+ return executeCode
+}};
diff --git a/src/arch/sparc/isa/formats/micro.isa b/src/arch/sparc/isa/formats/micro.isa
new file mode 100644
index 000000000..82d7fb4cb
--- /dev/null
+++ b/src/arch/sparc/isa/formats/micro.isa
@@ -0,0 +1,103 @@
+// Copyright (c) 2006 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Gabe Black
+
+output header {{
+
+ class SparcMacroInst : public SparcStaticInst
+ {
+ protected:
+ const uint32_t numMicroOps;
+
+ //Constructor.
+ SparcMacroInst(const char *mnem, ExtMachInst _machInst,
+ OpClass __opClass, uint32_t _numMicroOps)
+ : SparcStaticInst(mnem, _machInst, __opClass),
+ numMicroOps(_numMicroOps)
+ {
+ assert(numMicroOps);
+ microOps = new StaticInstPtr[numMicroOps];
+ flags[IsMacroOp] = true;
+ }
+
+ ~SparcMacroInst()
+ {
+ delete [] microOps;
+ }
+
+ std::string generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const;
+
+ StaticInstPtr * microOps;
+
+ StaticInstPtr fetchMicroOp(MicroPC microPC)
+ {
+ assert(microPC < numMicroOps);
+ return microOps[microPC];
+ }
+
+ %(BasicExecPanic)s
+ };
+
+ class SparcMicroInst : public SparcStaticInst
+ {
+ protected:
+ //Constructor.
+ SparcMicroInst(const char *mnem,
+ ExtMachInst _machInst, OpClass __opClass)
+ : SparcStaticInst(mnem, _machInst, __opClass)
+ {
+ flags[IsMicroOp] = true;
+ }
+ };
+
+ class SparcDelayedMicroInst : public SparcMicroInst
+ {
+ protected:
+ //Constructor.
+ SparcDelayedMicroInst(const char *mnem,
+ ExtMachInst _machInst, OpClass __opClass)
+ : SparcMicroInst(mnem, _machInst, __opClass)
+ {
+ flags[IsDelayedCommit] = true;
+ }
+ };
+}};
+
+output decoder {{
+
+ std::string SparcMacroInst::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
+ {
+ std::stringstream response;
+
+ printMnemonic(response, mnemonic);
+
+ return response.str();
+ }
+
+}};
diff --git a/src/arch/sparc/isa/formats/priv.isa b/src/arch/sparc/isa/formats/priv.isa
index d7ee01519..2a38422a7 100644
--- a/src/arch/sparc/isa/formats/priv.isa
+++ b/src/arch/sparc/isa/formats/priv.isa
@@ -103,13 +103,13 @@ let {{
(usesImm, code, immCode,
rString, iString) = splitOutImm(code)
iop = InstObjParams(name, Name, 'Priv', code,
- opt_flags, ("check", checkCode))
+ opt_flags, {"check": checkCode})
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
exec_output = PrivExecute.subst(iop)
if usesImm:
imm_iop = InstObjParams(name, Name + 'Imm', 'PrivImm',
- immCode, opt_flags, ("check", checkCode))
+ immCode, opt_flags, {"check": checkCode})
header_output += BasicDeclare.subst(imm_iop)
decoder_output += BasicConstructor.subst(imm_iop)
exec_output += PrivExecute.subst(imm_iop)
diff --git a/src/arch/sparc/isa/formats/unimp.isa b/src/arch/sparc/isa/formats/unimp.isa
new file mode 100644
index 000000000..a623507a1
--- /dev/null
+++ b/src/arch/sparc/isa/formats/unimp.isa
@@ -0,0 +1,147 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2003-2005 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Steve Reinhardt
+
+////////////////////////////////////////////////////////////////////
+//
+// Unimplemented instructions
+//
+
+output header {{
+ /**
+ * Static instruction class for unimplemented instructions that
+ * cause simulator termination. Note that these are recognized
+ * (legal) instructions that the simulator does not support; the
+ * 'Unknown' class is used for unrecognized/illegal instructions.
+ * This is a leaf class.
+ */
+ class FailUnimplemented : public SparcStaticInst
+ {
+ public:
+ /// Constructor
+ FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst)
+ : SparcStaticInst(_mnemonic, _machInst, No_OpClass)
+ {
+ // don't call execute() (which panics) if we're on a
+ // speculative path
+ flags[IsNonSpeculative] = true;
+ }
+
+ %(BasicExecDeclare)s
+
+ std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+
+ /**
+ * Base class for unimplemented instructions that cause a warning
+ * to be printed (but do not terminate simulation). This
+ * implementation is a little screwy in that it will print a
+ * warning for each instance of a particular unimplemented machine
+ * instruction, not just for each unimplemented opcode. Should
+ * probably make the 'warned' flag a static member of the derived
+ * class.
+ */
+ class WarnUnimplemented : public SparcStaticInst
+ {
+ private:
+ /// Have we warned on this instruction yet?
+ mutable bool warned;
+
+ public:
+ /// Constructor
+ WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst)
+ : SparcStaticInst(_mnemonic, _machInst, No_OpClass), warned(false)
+ {
+ // don't call execute() (which panics) if we're on a
+ // speculative path
+ flags[IsNonSpeculative] = true;
+ }
+
+ %(BasicExecDeclare)s
+
+ std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+}};
+
+output decoder {{
+ std::string
+ FailUnimplemented::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
+ {
+ return csprintf("%-10s (unimplemented)", mnemonic);
+ }
+
+ std::string
+ WarnUnimplemented::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
+ {
+#ifdef SS_COMPATIBLE_DISASSEMBLY
+ return csprintf("%-10s", mnemonic);
+#else
+ return csprintf("%-10s (unimplemented)", mnemonic);
+#endif
+ }
+}};
+
+output exec {{
+ Fault
+ FailUnimplemented::execute(%(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData) const
+ {
+ panic("attempt to execute unimplemented instruction '%s' "
+ "(inst 0x%08x)", mnemonic, machInst);
+ return NoFault;
+ }
+
+ Fault
+ WarnUnimplemented::execute(%(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData) const
+ {
+ if (!warned) {
+ warn("instruction '%s' unimplemented\n", mnemonic);
+ warned = true;
+ }
+
+ return NoFault;
+ }
+}};
+
+
+def format FailUnimpl() {{
+ iop = InstObjParams(name, 'FailUnimplemented')
+ decode_block = BasicDecodeWithMnemonic.subst(iop)
+}};
+
+def format WarnUnimpl() {{
+ iop = InstObjParams(name, 'WarnUnimplemented')
+ decode_block = BasicDecodeWithMnemonic.subst(iop)
+}};
+
diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa
index f1c2bee96..a324756ec 100644
--- a/src/arch/sparc/isa/includes.isa
+++ b/src/arch/sparc/isa/includes.isa
@@ -40,6 +40,7 @@ output header {{
#include "cpu/static_inst.hh"
#include "arch/sparc/faults.hh"
#include "mem/request.hh" // some constructors use MemReq flags
+#include "mem/packet.hh"
#include "arch/sparc/isa_traits.hh"
#include "arch/sparc/regfile.hh"
}};
@@ -48,6 +49,7 @@ output decoder {{
#include "base/cprintf.hh"
#include "base/loader/symtab.hh"
#include "cpu/thread_context.hh" // for Jump::branchTarget()
+#include "mem/packet.hh"
#if defined(linux)
#include <fenv.h>
@@ -65,6 +67,8 @@ output exec {{
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
#include "sim/sim_exit.hh"
+#include "mem/packet.hh"
+#include "mem/packet_access.hh"
using namespace SparcISA;
}};
diff --git a/src/arch/sparc/isa/main.isa b/src/arch/sparc/isa/main.isa
index 14acf54fa..df5ad0c99 100644
--- a/src/arch/sparc/isa/main.isa
+++ b/src/arch/sparc/isa/main.isa
@@ -26,7 +26,7 @@
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
-// Authors: Korey Sewell
+// Authors: Gabe Black
////////////////////////////////////////////////////////////////////
//
@@ -55,7 +55,7 @@ namespace SparcISA;
##include "base.isa"
//Include the definitions for the instruction formats
-##include "formats.isa"
+##include "formats/formats.isa"
//Include the decoder definition
##include "decoder.isa"
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa
index 605816083..b8b75170b 100644
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -42,6 +42,16 @@ def operand_types {{
'qf' : ('float', 128)
}};
+output header {{
+ // A function to "decompress" double and quad floating point
+ // register numbers stuffed into 5 bit fields. These have their
+ // MSB put in the LSB position but are otherwise normal.
+ static inline unsigned int dfpr(unsigned int regNum)
+ {
+ return (regNum & (~1)) | ((regNum & 1) << 5);
+ }
+}};
+
def operands {{
# Int regs default to unsigned, but code should not count on this.
# For clarity, descriptions that depend on unsigned behavior should
@@ -51,10 +61,22 @@ def operands {{
'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 3),
'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4),
'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5),
- 'Frd': ('FloatReg', 'df', 'RD', 'IsFloating', 10),
- 'Frs1': ('FloatReg', 'df', 'RS1', 'IsFloating', 11),
- 'Frs2': ('FloatReg', 'df', 'RS2', 'IsFloating', 12),
- 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 20),
+ 'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10),
+ 'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
+ # Each Frd_N refers to the Nth double precision register from Frd.
+ # Note that this adds twice N to the register number.
+ 'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
+ 'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10),
+ 'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10),
+ 'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10),
+ 'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10),
+ 'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10),
+ 'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10),
+ 'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10),
+ 'Frs1s': ('FloatReg', 'df', 'RS1', 'IsFloating', 11),
+ 'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11),
+ 'Frs2s': ('FloatReg', 'df', 'RS2', 'IsFloating', 12),
+ 'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),
'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31),
'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32),
#'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
@@ -84,6 +106,8 @@ def operands {{
'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 54),
'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 55),
- 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 56)
+ 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 56),
+ # Mem gets a large number so it's always last
+ 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
}};
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-15 16:41:26 +0000