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-rw-r--r--src/arch/sparc/isa/base.isa2
-rw-r--r--src/arch/sparc/isa/formats/basic.isa4
-rw-r--r--src/arch/sparc/isa/formats/branch.isa4
-rw-r--r--src/arch/sparc/isa/formats/integerop.isa2
-rw-r--r--src/arch/sparc/isa/formats/mem/swap.isa6
-rw-r--r--src/arch/sparc/isa/formats/mem/util.isa14
-rw-r--r--src/arch/sparc/isa/formats/nop.isa2
-rw-r--r--src/arch/sparc/isa/formats/priv.isa2
-rw-r--r--src/arch/sparc/isa/formats/trap.isa4
-rw-r--r--src/arch/sparc/isa/formats/unimp.isa4
-rw-r--r--src/arch/sparc/isa/formats/unknown.isa2
11 files changed, 23 insertions, 23 deletions
diff --git a/src/arch/sparc/isa/base.isa b/src/arch/sparc/isa/base.isa
index 3ff1d22b0..3c95c2638 100644
--- a/src/arch/sparc/isa/base.isa
+++ b/src/arch/sparc/isa/base.isa
@@ -564,7 +564,7 @@ output exec {{
/// @retval Full-system mode: NoFault if FP is enabled, FpDisabled
/// if not. Non-full-system mode: always returns NoFault.
static inline Fault
- checkFpEnableFault(%(CPU_exec_context)s *xc)
+ checkFpEnableFault(CPU_EXEC_CONTEXT *xc)
{
if (FullSystem) {
PSTATE pstate = xc->readMiscReg(MISCREG_PSTATE);
diff --git a/src/arch/sparc/isa/formats/basic.isa b/src/arch/sparc/isa/formats/basic.isa
index feb99e140..7d70e8e60 100644
--- a/src/arch/sparc/isa/formats/basic.isa
+++ b/src/arch/sparc/isa/formats/basic.isa
@@ -113,7 +113,7 @@ def template BasicConstructorWithMnemonic {{
// Basic instruction class execute method template.
def template BasicExecute {{
Fault
- %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -132,7 +132,7 @@ def template BasicExecute {{
def template DoFpOpExecute {{
Fault
- %(class_name)s::doFpOp(%(CPU_exec_context)s *xc,
+ %(class_name)s::doFpOp(CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
diff --git a/src/arch/sparc/isa/formats/branch.isa b/src/arch/sparc/isa/formats/branch.isa
index b34704f06..eb289931e 100644
--- a/src/arch/sparc/isa/formats/branch.isa
+++ b/src/arch/sparc/isa/formats/branch.isa
@@ -186,7 +186,7 @@ output decoder {{
}};
def template JumpExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
// Attempt to execute the instruction
@@ -208,7 +208,7 @@ def template JumpExecute {{
def template BranchExecute {{
Fault
- %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
// Attempt to execute the instruction
diff --git a/src/arch/sparc/isa/formats/integerop.isa b/src/arch/sparc/isa/formats/integerop.isa
index 58d7b37ee..355bbf393 100644
--- a/src/arch/sparc/isa/formats/integerop.isa
+++ b/src/arch/sparc/isa/formats/integerop.isa
@@ -237,7 +237,7 @@ output decoder {{
}};
def template IntOpExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
diff --git a/src/arch/sparc/isa/formats/mem/swap.isa b/src/arch/sparc/isa/formats/mem/swap.isa
index 17a490c4b..34dabc8cb 100644
--- a/src/arch/sparc/isa/formats/mem/swap.isa
+++ b/src/arch/sparc/isa/formats/mem/swap.isa
@@ -29,7 +29,7 @@
// This template provides the execute functions for a swap
def template SwapExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -68,7 +68,7 @@ def template SwapExecute {{
def template SwapInitiateAcc {{
- Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
+ Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT * xc,
Trace::InstRecord * traceData) const
{
Fault fault = NoFault;
@@ -97,7 +97,7 @@ def template SwapInitiateAcc {{
def template SwapCompleteAcc {{
- Fault %(class_name)s::completeAcc(PacketPtr pkt, %(CPU_exec_context)s * xc,
+ Fault %(class_name)s::completeAcc(PacketPtr pkt, CPU_EXEC_CONTEXT * xc,
Trace::InstRecord * traceData) const
{
Fault fault = NoFault;
diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa
index ffce3063b..cf0a62ed9 100644
--- a/src/arch/sparc/isa/formats/mem/util.isa
+++ b/src/arch/sparc/isa/formats/mem/util.isa
@@ -130,7 +130,7 @@ output decoder {{
// This template provides the execute functions for a load
def template LoadExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -158,7 +158,7 @@ def template LoadExecute {{
}};
def template LoadInitiateAcc {{
- Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
+ Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT * xc,
Trace::InstRecord * traceData) const
{
Fault fault = NoFault;
@@ -178,7 +178,7 @@ def template LoadInitiateAcc {{
}};
def template LoadCompleteAcc {{
- Fault %(class_name)s::completeAcc(PacketPtr pkt, %(CPU_exec_context)s * xc,
+ Fault %(class_name)s::completeAcc(PacketPtr pkt, CPU_EXEC_CONTEXT * xc,
Trace::InstRecord * traceData) const
{
Fault fault = NoFault;
@@ -195,7 +195,7 @@ def template LoadCompleteAcc {{
// This template provides the execute functions for a store
def template StoreExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -226,7 +226,7 @@ def template StoreExecute {{
}};
def template StoreInitiateAcc {{
- Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
+ Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT * xc,
Trace::InstRecord * traceData) const
{
Fault fault = NoFault;
@@ -251,7 +251,7 @@ def template StoreInitiateAcc {{
}};
def template StoreCompleteAcc {{
- Fault %(class_name)s::completeAcc(PacketPtr, %(CPU_exec_context)s * xc,
+ Fault %(class_name)s::completeAcc(PacketPtr, CPU_EXEC_CONTEXT * xc,
Trace::InstRecord * traceData) const
{
return NoFault;
@@ -260,7 +260,7 @@ def template StoreCompleteAcc {{
def template EACompExecute {{
Fault
- %(class_name)s::eaComp(%(CPU_exec_context)s *xc,
+ %(class_name)s::eaComp(CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
diff --git a/src/arch/sparc/isa/formats/nop.isa b/src/arch/sparc/isa/formats/nop.isa
index a1c650369..aab1f198d 100644
--- a/src/arch/sparc/isa/formats/nop.isa
+++ b/src/arch/sparc/isa/formats/nop.isa
@@ -79,7 +79,7 @@ output decoder {{
}};
def template NopExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
// Nothing to see here, move along
diff --git a/src/arch/sparc/isa/formats/priv.isa b/src/arch/sparc/isa/formats/priv.isa
index c12a31b10..b52637f81 100644
--- a/src/arch/sparc/isa/formats/priv.isa
+++ b/src/arch/sparc/isa/formats/priv.isa
@@ -195,7 +195,7 @@ def template ControlRegConstructor {{
}};
def template PrivExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
%(op_decl)s;
diff --git a/src/arch/sparc/isa/formats/trap.isa b/src/arch/sparc/isa/formats/trap.isa
index 018379f57..bda7d5192 100644
--- a/src/arch/sparc/isa/formats/trap.isa
+++ b/src/arch/sparc/isa/formats/trap.isa
@@ -72,7 +72,7 @@ output decoder {{
def template TrapExecute {{
Fault
- %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -85,7 +85,7 @@ def template TrapExecute {{
def template FpUnimplExecute {{
Fault
- %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
diff --git a/src/arch/sparc/isa/formats/unimp.isa b/src/arch/sparc/isa/formats/unimp.isa
index 927bf9e64..bd87942ad 100644
--- a/src/arch/sparc/isa/formats/unimp.isa
+++ b/src/arch/sparc/isa/formats/unimp.isa
@@ -109,7 +109,7 @@ output decoder {{
output exec {{
Fault
- FailUnimplemented::execute(%(CPU_exec_context)s *xc,
+ FailUnimplemented::execute(CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
panic("attempt to execute unimplemented instruction '%s' "
@@ -118,7 +118,7 @@ output exec {{
}
Fault
- WarnUnimplemented::execute(%(CPU_exec_context)s *xc,
+ WarnUnimplemented::execute(CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
if (!warned) {
diff --git a/src/arch/sparc/isa/formats/unknown.isa b/src/arch/sparc/isa/formats/unknown.isa
index 8541d6a62..5b2db2b57 100644
--- a/src/arch/sparc/isa/formats/unknown.isa
+++ b/src/arch/sparc/isa/formats/unknown.isa
@@ -63,7 +63,7 @@ output decoder {{
}};
output exec {{
- Fault Unknown::execute(%(CPU_exec_context)s *xc,
+ Fault Unknown::execute(CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
return new IllegalInstruction;
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-07 15:11:59 +0000