7 files changed, 112 insertions, 89 deletions
diff --git a/src/arch/sparc/isa/base.isa b/src/arch/sparc/isa/base.isa
index aa24c75be..4a806bfd0 100644
--- a/src/arch/sparc/isa/base.isa
+++ b/src/arch/sparc/isa/base.isa
@@ -205,7 +205,7 @@ output decoder {{
             else if(reg < MaxMicroReg)
                 ccprintf(os, "%%u%d", reg - MaxInput);
             else {
-                ccprintf(os, "%%f%d", reg - FP_Base_DepTag);
+                ccprintf(os, "%%f%d", reg - MaxMicroReg);
             }
         }
 
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index 2c8e59a1d..7a48042c2 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -307,7 +307,7 @@ decode OP default Unknown::unknown()
                 int64_t resTemp, val2 = Rs2_or_imm13;
                 Rd = resTemp = Rs1 + val2;
                 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
-                {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
+                {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
                 {{overflow}},
                 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
                 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
@@ -316,7 +316,7 @@ decode OP default Unknown::unknown()
                 int64_t resTemp, val2 = Rs2_or_imm13;
                 Rd = resTemp = Rs1 + val2;
                 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
-                {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31}},
+                {{(Rs1<31:0> + val2<31:0>)<32:0>}},
                 {{overflow}},
                 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
                 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
@@ -327,7 +327,7 @@ decode OP default Unknown::unknown()
                 int32_t overflow = Rs1<1:0> || val2<1:0> ||
                         (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>);
                 if(overflow) fault = new TagOverflow;}},
-                {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
+                {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
                 {{overflow}},
                 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
                 {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}}
@@ -337,7 +337,7 @@ decode OP default Unknown::unknown()
                 Rd = resTemp = Rs1 + val2;
                 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
                 if(overflow) fault = new TagOverflow;}},
-                {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
+                {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
                 {{overflow}},
                 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
                 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
@@ -347,13 +347,12 @@ decode OP default Unknown::unknown()
                 int32_t multiplier = Rs1<31:0>;
                 int32_t savedLSB = Rs1<0:>;
                 multiplier = multiplier<31:1> |
-                    ((Ccr<3:3>
-                    ^ Ccr<1:1>) << 32);
+                    ((Ccr<3:3> ^ Ccr<1:1>) << 32);
                 if(!Y<0:>)
                     multiplicand = 0;
                 Rd = resTemp = multiplicand + multiplier;
                 Y = Y<31:1> | (savedLSB << 31);}},
-                {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}},
+                {{((multiplicand<31:0> + multiplier<31:0>)<32:0>)}},
                 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
                 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
                 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
@@ -527,7 +526,7 @@ decode OP default Unknown::unknown()
                 0x00: NoPriv::wry({{Y = Rs1 ^ Rs2_or_imm13;}});
                 //0x01 should cause an illegal instruction exception
                 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
-                0x03: NoPriv::wrasi({{Ccr = Rs1 ^ Rs2_or_imm13;}});
+                0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}});
                 //0x04-0x05 should cause an illegal instruction exception
                 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}});
                 //0x07-0x0E should cause an illegal instruction exception
@@ -1005,6 +1004,7 @@ decode OP default Unknown::unknown()
                     Asi = Tstate<31:24>;
                     Ccr = Tstate<39:32>;
                     Gl = Tstate<42:40>;
+                    Hpstate = Htstate;
                     NPC = Tnpc;
                     NNPC = Tnpc + 4;
                     Tl = Tl - 1;
@@ -1017,6 +1017,7 @@ decode OP default Unknown::unknown()
                     Asi = Tstate<31:24>;
                     Ccr = Tstate<39:32>;
                     Gl = Tstate<42:40>;
+                    Hpstate = Htstate;
                     NPC = Tpc;
                     NNPC = Tnpc;
                     Tl = Tl - 1;
@@ -1055,36 +1056,36 @@ decode OP default Unknown::unknown()
             {{uReg0 = Rd.uw;
             Rd.uw = Mem.uw;}},
             {{Mem.uw = uReg0;}});
-        format Load {
-            0x10: lduwa({{Rd = Mem.uw;}});
-            0x11: lduba({{Rd = Mem.ub;}});
-            0x12: lduha({{Rd = Mem.uhw;}});
+        format LoadAlt {
+            0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}});
+            0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}});
+            0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}});
             0x13: ldda({{
                 uint64_t val = Mem.udw;
                 RdLow = val<31:0>;
                 RdHigh = val<63:32>;
-            }});
+            }}, {{EXT_ASI}});
         }
-        format Store {
-            0x14: stwa({{Mem.uw = Rd;}});
-            0x15: stba({{Mem.ub = Rd;}});
-            0x16: stha({{Mem.uhw = Rd;}});
-            0x17: stda({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}});
+        format StoreAlt {
+            0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}});
+            0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}});
+            0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}});
+            0x17: stda({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{EXT_ASI}});
         }
-        format Load {
-            0x18: ldswa({{Rd = (int32_t)Mem.sw;}});
-            0x19: ldsba({{Rd = (int8_t)Mem.sb;}});
-            0x1A: ldsha({{Rd = (int16_t)Mem.shw;}});
-            0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}});
+        format LoadAlt {
+            0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}});
+            0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}});
+            0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}});
+            0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}});
         }
-        0x1D: LoadStore::ldstuba(
+        0x1D: LoadStoreAlt::ldstuba(
                 {{Rd = Mem.ub;}},
-                {{Mem.ub = 0xFF}});
-        0x1E: Store::stxa({{Mem.udw = Rd}});
-        0x1F: LoadStore::swapa(
+                {{Mem.ub = 0xFF}}, {{EXT_ASI}});
+        0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}});
+        0x1F: LoadStoreAlt::swapa(
             {{uReg0 = Rd.uw;
             Rd.uw = Mem.uw;}},
-            {{Mem.uw = uReg0;}});
+            {{Mem.uw = uReg0;}}, {{EXT_ASI}});
         format Trap {
             0x20: Load::ldf({{Frd.uw = Mem.uw;}});
             0x21: decode X {
@@ -1101,7 +1102,7 @@ decode OP default Unknown::unknown()
             0x26: stqf({{fault = new FpDisabled;}});
             0x27: Store::stdf({{Mem.udw = Frd.udw;}});
             0x2D: Nop::prefetch({{ }});
-            0x30: Load::ldfa({{Frd.uw = Mem.uw;}});
+            0x30: LoadAlt::ldfa({{Frd.uw = Mem.uw;}}, {{EXT_ASI}});
             0x32: ldqfa({{fault = new FpDisabled;}});
             format LoadAlt {
                 0x33: decode EXT_ASI {
@@ -1153,7 +1154,7 @@ decode OP default Unknown::unknown()
                         //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
                         0x1F: FailUnimpl::ldblockf_aiusl();
                         //ASI_BLOCK_PRIMARY
-                        0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}});
+                        0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}, {{EXT_ASI}});
                         //ASI_BLOCK_SECONDARY
                         0xF1: FailUnimpl::ldblockf_s();
                         //ASI_BLOCK_PRIMARY_LITTLE
@@ -1236,7 +1237,7 @@ decode OP default Unknown::unknown()
                         //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
                         0x1F: FailUnimpl::stblockf_aiusl();
                         //ASI_BLOCK_PRIMARY
-                        0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}});
+                        0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}, {{EXT_ASI}});
                         //ASI_BLOCK_SECONDARY
                         0xF1: FailUnimpl::stblockf_s();
                         //ASI_BLOCK_PRIMARY_LITTLE
@@ -1273,7 +1274,7 @@ decode OP default Unknown::unknown()
                         Mem.uw = Rd.uw;
                 else
                         storeCond = false;
-                Rd.uw = uReg0;}});
+                Rd.uw = uReg0;}}, {{EXT_ASI}});
             0x3D: Nop::prefetcha({{ }});
             0x3E: Cas::casxa(
                 {{uReg0 = Mem.udw;}},
@@ -1281,7 +1282,7 @@ decode OP default Unknown::unknown()
                         Mem.udw = Rd;
                 else
                         storeCond = false;
-                Rd = uReg0;}});
+                Rd = uReg0;}}, {{EXT_ASI}});
         }
     }
 }
diff --git a/src/arch/sparc/isa/formats/mem/basicmem.isa b/src/arch/sparc/isa/formats/mem/basicmem.isa
index cb6c2f161..55e9fba45 100644
--- a/src/arch/sparc/isa/formats/mem/basicmem.isa
+++ b/src/arch/sparc/isa/formats/mem/basicmem.isa
@@ -52,7 +52,7 @@ def template MemDeclare {{
 }};
 
 let {{
-    def doMemFormat(code, execute, faultCode, name, Name, opt_flags):
+    def doMemFormat(code, execute, faultCode, name, Name, asi, opt_flags):
         addrCalcReg = 'EA = Rs1 + Rs2;'
         addrCalcImm = 'EA = Rs1 + imm;'
         iop = InstObjParams(name, Name, 'Mem', code,
@@ -62,25 +62,26 @@ let {{
         header_output = MemDeclare.subst(iop) + MemDeclare.subst(iop_imm)
         decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm)
         decode_block = ROrImmDecode.subst(iop)
-        exec_output = doDualSplitExecute(code, addrCalcReg, addrCalcImm, execute,
-                faultCode, name, name + "Imm", Name, Name + "Imm", opt_flags)
+        exec_output = doDualSplitExecute(code, addrCalcReg, addrCalcImm,
+                execute, faultCode, name, name + "Imm", Name, Name + "Imm",
+                asi, opt_flags)
         return (header_output, decoder_output, exec_output, decode_block)
 }};
 
-def format LoadAlt(code, *opt_flags) {{
+def format LoadAlt(code, asi, *opt_flags) {{
         (header_output,
          decoder_output,
          exec_output,
          decode_block) = doMemFormat(code, LoadExecute,
-            AlternateAsiPrivFaultCheck, name, Name, opt_flags)
+            AlternateASIPrivFaultCheck, name, Name, asi, opt_flags)
 }};
 
-def format StoreAlt(code, *opt_flags) {{
+def format StoreAlt(code, asi, *opt_flags) {{
         (header_output,
          decoder_output,
          exec_output,
          decode_block) = doMemFormat(code, StoreExecute,
-            AlternateAsiPrivFaultCheck, name, Name, opt_flags)
+            AlternateASIPrivFaultCheck, name, Name, asi, opt_flags)
 }};
 
 def format Load(code, *opt_flags) {{
@@ -88,7 +89,7 @@ def format Load(code, *opt_flags) {{
          decoder_output,
          exec_output,
          decode_block) = doMemFormat(code,
-             LoadExecute, '', name, Name, opt_flags)
+             LoadExecute, '', name, Name, 0, opt_flags)
 }};
 
 def format Store(code, *opt_flags) {{
@@ -96,5 +97,5 @@ def format Store(code, *opt_flags) {{
          decoder_output,
          exec_output,
          decode_block) = doMemFormat(code,
-             StoreExecute, '', name, Name, opt_flags)
+             StoreExecute, '', name, Name, 0, opt_flags)
 }};
diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa
index 8b4aca473..7a1a58d13 100644
--- a/src/arch/sparc/isa/formats/mem/blockmem.isa
+++ b/src/arch/sparc/isa/formats/mem/blockmem.isa
@@ -273,7 +273,7 @@ def template BlockMemMicroConstructor {{
 
 let {{
 
-    def doBlockMemFormat(code, faultCode, execute, name, Name, opt_flags):
+    def doBlockMemFormat(code, faultCode, execute, name, Name, asi, opt_flags):
         # XXX Need to take care of pstate.hpriv as well. The lower ASIs
         # are split into ones that are available in priv and hpriv, and
         # those that are only available in hpriv
@@ -309,12 +309,12 @@ let {{
                     makeMicroName(name + "Imm", microPc),
                     makeMicroName(Name, microPc),
                     makeMicroName(Name + "Imm", microPc),
-                    opt_flags);
+                    asi, opt_flags);
             faultCode = ''
         return (header_output, decoder_output, exec_output, decode_block)
 }};
 
-def format BlockLoad(code, *opt_flags) {{
+def format BlockLoad(code, asi, *opt_flags) {{
         # We need to make sure to check the highest priority fault last.
         # That way, if other faults have been detected, they'll be overwritten
         # rather than the other way around.
@@ -323,10 +323,10 @@ def format BlockLoad(code, *opt_flags) {{
          decoder_output,
          exec_output,
          decode_block) = doBlockMemFormat(code, faultCode,
-             LoadExecute, name, Name, opt_flags)
+             LoadExecute, name, Name, asi, opt_flags)
 }};
 
-def format BlockStore(code, *opt_flags) {{
+def format BlockStore(code, asi, *opt_flags) {{
         # We need to make sure to check the highest priority fault last.
         # That way, if other faults have been detected, they'll be overwritten
         # rather than the other way around.
@@ -335,5 +335,5 @@ def format BlockStore(code, *opt_flags) {{
          decoder_output,
          exec_output,
          decode_block) = doBlockMemFormat(code, faultCode,
-             StoreExecute, name, Name, opt_flags)
+             StoreExecute, name, Name, asi, opt_flags)
 }};
diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa
index b9f7fde2d..3e9fd7a7d 100644
--- a/src/arch/sparc/isa/formats/mem/util.isa
+++ b/src/arch/sparc/isa/formats/mem/util.isa
@@ -76,19 +76,22 @@ output decoder {{
         {
             std::stringstream response;
             bool load = flags[IsLoad];
-            bool save = flags[IsStore];
+            bool store = flags[IsStore];
 
             printMnemonic(response, mnemonic);
-            if(save)
+            if(store)
             {
                 printReg(response, _srcRegIdx[0]);
                 ccprintf(response, ", ");
             }
-            ccprintf(response, "[ ");
-            printReg(response, _srcRegIdx[!save ? 0 : 1]);
-            ccprintf(response, " + ");
-            printReg(response, _srcRegIdx[!save ? 1 : 2]);
-            ccprintf(response, " ]");
+            ccprintf(response, "[");
+            if(_srcRegIdx[!store ? 0 : 1] != 0)
+            {
+                printSrcReg(response, !store ? 0 : 1);
+                ccprintf(response, " + ");
+            }
+            printSrcReg(response, !store ? 1 : 2);
+            ccprintf(response, "]");
             if(load)
             {
                 ccprintf(response, ", ");
@@ -111,12 +114,16 @@ output decoder {{
                 printReg(response, _srcRegIdx[0]);
                 ccprintf(response, ", ");
             }
-            ccprintf(response, "[ ");
-            printReg(response, _srcRegIdx[!save ? 0 : 1]);
+            ccprintf(response, "[");
+            if(_srcRegIdx[!save ? 0 : 1] != 0)
+            {
+                printReg(response, _srcRegIdx[!save ? 0 : 1]);
+                ccprintf(response, " + ");
+            }
             if(imm >= 0)
-                ccprintf(response, " + 0x%x ]", imm);
+                ccprintf(response, "0x%x]", imm);
             else
-                ccprintf(response, " + -0x%x ]", -imm);
+                ccprintf(response, "-0x%x]", -imm);
             if(load)
             {
                 ccprintf(response, ", ");
@@ -141,7 +148,7 @@ def template LoadExecute {{
             %(fault_check)s;
             if(fault == NoFault)
             {
-                fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, 0);
+                fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, %(asi_val)s);
             }
             if(fault == NoFault)
             {
@@ -149,8 +156,8 @@ def template LoadExecute {{
             }
             if(fault == NoFault)
             {
-                //Write the resulting state to the execution context
-                %(op_wb)s;
+                    //Write the resulting state to the execution context
+                    %(op_wb)s;
             }
 
             return fault;
@@ -168,7 +175,7 @@ def template LoadExecute {{
             %(fault_check)s;
             if(fault == NoFault)
             {
-                fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, 0);
+                fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, %(asi_val)s);
             }
             return fault;
         }
@@ -195,7 +202,6 @@ def template StoreExecute {{
                 Trace::InstRecord *traceData) const
         {
             Fault fault = NoFault;
-            uint64_t write_result = 0;
             //This is to support the conditional store in cas instructions.
             //It should be optomized out in all the others
             bool storeCond = true;
@@ -211,12 +217,13 @@ def template StoreExecute {{
             }
             if(storeCond && fault == NoFault)
             {
-                fault = xc->write((uint%(mem_acc_size)s_t)Mem, EA, 0, &write_result);
+                fault = xc->write((uint%(mem_acc_size)s_t)Mem,
+                        EA, %(asi_val)s, 0);
             }
             if(fault == NoFault)
             {
-                //Write the resulting state to the execution context
-                %(op_wb)s;
+                    //Write the resulting state to the execution context
+                    %(op_wb)s;
             }
 
             return fault;
@@ -226,7 +233,6 @@ def template StoreExecute {{
                 Trace::InstRecord * traceData) const
         {
             Fault fault = NoFault;
-            uint64_t write_result = 0;
             bool storeCond = true;
             Addr EA;
             %(op_decl)s;
@@ -240,11 +246,12 @@ def template StoreExecute {{
             }
             if(storeCond && fault == NoFault)
             {
-                fault = xc->write((uint%(mem_acc_size)s_t)Mem, EA, 0, &write_result);
+                fault = xc->write((uint%(mem_acc_size)s_t)Mem,
+                        EA, %(asi_val)s, 0);
             }
             if(fault == NoFault)
             {
-                //Write the resulting state to the execution context
+                    //Write the resulting state to the execution context
                 %(op_wb)s;
             }
             return fault;
@@ -281,8 +288,9 @@ let {{
     # are split into ones that are available in priv and hpriv, and
     # those that are only available in hpriv
     AlternateASIPrivFaultCheck = '''
-        if(bits(Pstate,2,2) == 0 && (EXT_ASI & 0x80) == 0)
-            fault = new PrivilegedAction;
+        if(!bits(Pstate,2,2) && !bits(Hpstate,2,2) && !AsiIsUnPriv((ASI)EXT_ASI) ||
+                             !bits(Hpstate,2,2) && AsiIsHPriv((ASI)EXT_ASI))
+                fault = new PrivilegedAction;
         else if(AsiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2))
             fault = new PrivilegedAction;
     '''
@@ -293,7 +301,7 @@ let {{
 //instruction at a certain micropc
 let {{
     def makeMicroName(name, microPc):
-        return name + "::" + name + "_" + str(microPc)
+            return name + "::" + name + "_" + str(microPc)
 }};
 
 //This function properly generates the execute functions for one of the
@@ -302,13 +310,14 @@ let {{
 //and in the other they're distributed across two. Also note that for
 //execute functions, the name of the base class doesn't matter.
 let {{
-    def doSplitExecute(code, eaCode, execute,
-            faultCode, name, Name, opt_flags):
-        codeIop = InstObjParams(name, Name, '', code, opt_flags)
-        eaIop = InstObjParams(name, Name, '', eaCode,
-                opt_flags, {"fault_check": faultCode})
-        iop = InstObjParams(name, Name, '', code, opt_flags,
-                {"fault_check": faultCode, "ea_code" : eaCode})
+    def doSplitExecute(code, execute, name, Name, asi, opt_flags, microParam):
+        microParam["asi_val"] = asi;
+        codeParam = microParam.copy()
+        codeParam["ea_code"] = ''
+        codeIop = InstObjParams(name, Name, '', code, opt_flags, codeParam)
+        eaIop = InstObjParams(name, Name, '', microParam["ea_code"],
+                opt_flags, microParam)
+        iop = InstObjParams(name, Name, '', code, opt_flags, microParam)
         (iop.ea_decl,
          iop.ea_rd,
          iop.ea_wb) = (eaIop.op_decl, eaIop.op_rd, eaIop.op_wb)
@@ -319,12 +328,13 @@ let {{
 
 
     def doDualSplitExecute(code, eaRegCode, eaImmCode, execute,
-            faultCode, nameReg, nameImm, NameReg, NameImm, opt_flags):
+            faultCode, nameReg, nameImm, NameReg, NameImm, asi, opt_flags):
         executeCode = ''
         for (eaCode, name, Name) in (
                 (eaRegCode, nameReg, NameReg),
                 (eaImmCode, nameImm, NameImm)):
-            executeCode += doSplitExecute(code, eaCode,
-                    execute, faultCode, name, Name, opt_flags)
+            microParams = {"ea_code" : eaCode, "fault_check": faultCode}
+            executeCode += doSplitExecute(code, execute, name, Name,
+                    asi, opt_flags, microParams)
         return executeCode
 }};
diff --git a/src/arch/sparc/isa/formats/priv.isa b/src/arch/sparc/isa/formats/priv.isa
index 94a68aebe..3d47ca02f 100644
--- a/src/arch/sparc/isa/formats/priv.isa
+++ b/src/arch/sparc/isa/formats/priv.isa
@@ -153,8 +153,13 @@ output decoder {{
             printMnemonic(response, mnemonic);
 
             ccprintf(response, " ");
-            printSrcReg(response, 0);
-            ccprintf(response, ", ");
+            //If the first reg is %g0, don't print it.
+            //This improves readability
+            if(_srcRegIdx[0] != 0)
+            {
+                printSrcReg(response, 0);
+                ccprintf(response, ", ");
+            }
             printSrcReg(response, 1);
             ccprintf(response, ", %%%s", regName);
 
@@ -169,8 +174,14 @@ output decoder {{
             printMnemonic(response, mnemonic);
 
             ccprintf(response, " ");
-            printSrcReg(response, 0);
-            ccprintf(response, ", 0x%x, %%%s", imm, regName);
+            //If the first reg is %g0, don't print it.
+            //This improves readability
+            if(_srcRegIdx[0] != 0)
+            {
+                printSrcReg(response, 0);
+                ccprintf(response, ", ");
+            }
+            ccprintf(response, "0x%x, %%%s", imm, regName);
 
             return response.str();
         }
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa
index 2d200f568..80ed7362c 100644
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -61,7 +61,7 @@ def operands {{
     'RdHigh':		('IntReg', 'udw', 'RD | 1', 'IsInteger', 3),
     'Rs1': 		('IntReg', 'udw', 'RS1', 'IsInteger', 4),
     'Rs2': 		('IntReg', 'udw', 'RS2', 'IsInteger', 5),
-    'uReg0':		('IntReg', 'udw', 'NumRegularIntRegs+0', 'IsInteger', 6),
+    'uReg0':		('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 6),
     'Frds':		('FloatReg', 'sf', 'RD', 'IsFloating', 10),
     'Frd':		('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
     # Each Frd_N refers to the Nth double precision register from Frd.