diff options
Diffstat (limited to 'src/arch/sparc/isa')
| -rw-r--r-- | src/arch/sparc/isa/decoder.isa | 76 | ||||
| -rw-r--r-- | src/arch/sparc/isa/includes.isa | 1 | ||||
| -rw-r--r-- | src/arch/sparc/isa/operands.isa | 4 |
3 files changed, 40 insertions, 41 deletions
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index 8c23d5f03..6ca52c406 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -1102,8 +1102,8 @@ decode OP default Unknown::unknown() 0x01: ldub({{Rd = Mem_ub;}}); 0x02: lduh({{Rd = Mem_uhw;}}); 0x03: ldtw({{ - RdLow = (Mem_tuw).a; - RdHigh = (Mem_tuw).b; + RdLow = Mem_tuw[0]; + RdHigh = Mem_tuw[1]; }}); } format Store { @@ -1115,9 +1115,9 @@ decode OP default Unknown::unknown() // will correctly identify this instruction as a store. // It's probably either the parenthesis or referencing // the member variable that throws confuses it. - Twin32_t temp; - temp.a = RdLow<31:0>; - temp.b = RdHigh<31:0>; + std::array<uint32_t, 2> temp; + temp[0] = RdLow<31:0>; + temp[1] = RdHigh<31:0>; Mem_tuw = temp; }}); } @@ -1145,63 +1145,63 @@ decode OP default Unknown::unknown() 0x13: decode EXT_ASI { // ASI_LDTD_AIUP 0x22: TwinLoad::ldtx_aiup( - {{RdLow_udw = (Mem_tudw).a; - RdHigh_udw = (Mem_tudw).b;}}); + {{RdLow_udw = Mem_tudw[0]; + RdHigh_udw = Mem_tudw[1];}}); // ASI_LDTD_AIUS 0x23: TwinLoad::ldtx_aius( - {{RdLow_udw = (Mem_tudw).a; - RdHigh_udw = (Mem_tudw).b;}}); + {{RdLow_udw = Mem_tudw[0]; + RdHigh_udw = Mem_tudw[1];}}); // ASI_QUAD_LDD 0x24: TwinLoad::ldtx_quad_ldd( - {{RdLow_udw = (Mem_tudw).a; - RdHigh_udw = (Mem_tudw).b;}}); + {{RdLow_udw = Mem_tudw[0]; + RdHigh_udw = Mem_tudw[1];}}); // ASI_LDTX_REAL 0x26: TwinLoad::ldtx_real( - {{RdLow_udw = (Mem_tudw).a; - RdHigh_udw = (Mem_tudw).b;}}); + {{RdLow_udw = Mem_tudw[0]; + RdHigh_udw = Mem_tudw[1];}}); // ASI_LDTX_N 0x27: TwinLoad::ldtx_n( - {{RdLow_udw = (Mem_tudw).a; - RdHigh_udw = (Mem_tudw).b;}}); + {{RdLow_udw = Mem_tudw[0]; + RdHigh_udw = Mem_tudw[1];}}); // ASI_LDTX_AIUP_L 0x2A: TwinLoad::ldtx_aiup_l( - {{RdLow_udw = (Mem_tudw).a; - RdHigh_udw = (Mem_tudw).b;}}); + {{RdLow_udw = Mem_tudw[0]; + RdHigh_udw = Mem_tudw[1];}}); // ASI_LDTX_AIUS_L 0x2B: TwinLoad::ldtx_aius_l( - {{RdLow_udw = (Mem_tudw).a; - RdHigh_udw = (Mem_tudw).b;}}); + {{RdLow_udw = Mem_tudw[0]; + RdHigh_udw = Mem_tudw[1];}}); // ASI_LDTX_L 0x2C: TwinLoad::ldtx_l( - {{RdLow_udw = (Mem_tudw).a; - RdHigh_udw = (Mem_tudw).b;}}); + {{RdLow_udw = Mem_tudw[0]; + RdHigh_udw = Mem_tudw[1];}}); // ASI_LDTX_REAL_L 0x2E: TwinLoad::ldtx_real_l( - {{RdLow_udw = (Mem_tudw).a; - RdHigh_udw = (Mem_tudw).b;}}); + {{RdLow_udw = Mem_tudw[0]; + RdHigh_udw = Mem_tudw[1];}}); // ASI_LDTX_N_L 0x2F: TwinLoad::ldtx_n_l( - {{RdLow_udw = (Mem_tudw).a; - RdHigh_udw = (Mem_tudw).b;}}); + {{RdLow_udw = Mem_tudw[0]; + RdHigh_udw = Mem_tudw[1];}}); // ASI_LDTX_P 0xE2: TwinLoad::ldtx_p( - {{RdLow_udw = (Mem_tudw).a; - RdHigh_udw = (Mem_tudw).b;}}); + {{RdLow_udw = Mem_tudw[0]; + RdHigh_udw = Mem_tudw[1];}}); // ASI_LDTX_S 0xE3: TwinLoad::ldtx_s( - {{RdLow_udw = (Mem_tudw).a; - RdHigh_udw = (Mem_tudw).b;}}); + {{RdLow_udw = Mem_tudw[0]; + RdHigh_udw = Mem_tudw[1];}}); // ASI_LDTX_PL 0xEA: TwinLoad::ldtx_pl( - {{RdLow_udw = (Mem_tudw).a; - RdHigh_udw = (Mem_tudw).b;}}); + {{RdLow_udw = Mem_tudw[0]; + RdHigh_udw = Mem_tudw[1];}}); // ASI_LDTX_SL 0xEB: TwinLoad::ldtx_sl( - {{RdLow_udw = (Mem_tudw).a; - RdHigh_udw = (Mem_tudw).b;}}); + {{RdLow_udw = Mem_tudw[0]; + RdHigh_udw = Mem_tudw[1];}}); default: ldtwa({{ - RdLow = (Mem_tuw).a; - RdHigh = (Mem_tuw).b;}}); + RdLow = Mem_tuw[0]; + RdHigh = Mem_tuw[1];}}); } } format StoreAlt { @@ -1213,9 +1213,9 @@ decode OP default Unknown::unknown() // will correctly identify this instruction as a store. // It's probably either the parenthesis or referencing // the member variable that throws confuses it. - Twin32_t temp; - temp.a = RdLow<31:0>; - temp.b = RdHigh<31:0>; + std::array<uint32_t, 2> temp; + temp[0] = RdLow<31:0>; + temp[1] = RdHigh<31:0>; Mem_tuw = temp; }}); } diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa index ff48b0aec..0ff93a873 100644 --- a/src/arch/sparc/isa/includes.isa +++ b/src/arch/sparc/isa/includes.isa @@ -80,7 +80,6 @@ output exec {{ #include "arch/generic/memhelpers.hh" #include "arch/sparc/asi.hh" -#include "base/bigint.hh" #include "cpu/base.hh" #include "cpu/exetrace.hh" #include "debug/Sparc.hh" diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa index 32a39bbee..26c0d87a7 100644 --- a/src/arch/sparc/isa/operands.isa +++ b/src/arch/sparc/isa/operands.isa @@ -37,8 +37,8 @@ def operand_types {{ 'uw' : 'uint32_t', 'sdw' : 'int64_t', 'udw' : 'uint64_t', - 'tudw' : 'Twin64_t', - 'tuw' : 'Twin32_t', + 'tudw' : 'std::array<uint64_t, 2>', + 'tuw' : 'std::array<uint32_t, 2>', 'sf' : 'float', 'df' : 'double', |