1 files changed, 13 insertions, 6 deletions

diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index 93737ad01..d2164155f 100644
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -50,7 +50,7 @@ class Checkpoint;
 string SparcISA::getMiscRegName(RegIndex index)
 {
     static::string miscRegName[NumMiscRegs] =
-        {"y", "ccr", "asi", "tick", "pc", "fprs", "pcr", "pic",
+        {"y", "ccr", "asi", "tick", "fprs", "pcr", "pic",
          "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
          "stick", "stick_cmpr",
          "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
@@ -62,7 +62,12 @@ string SparcISA::getMiscRegName(RegIndex index)
     return miscRegName[index];
 }
 
-void MiscRegFile::reset()
+enum RegMask
+{
+        PSTATE_MASK = (((1 << 4) - 1) << 1) | (((1 << 4) - 1) << 6) | (1 << 12)
+};
+
+void MiscRegFile::clear()
 {
     y = 0;
     ccr = 0;
@@ -88,12 +93,14 @@ void MiscRegFile::reset()
     otherwin = 0;
     wstate = 0;
     gl = 0;
-    hpstate = 0;
+    //In a T1, bit 11 is apparently always 1
+    hpstate = (1 << 11);
     memset(htstate, 0, sizeof(htstate));
     hintp = 0;
     htba = 0;
     hstick_cmpr = 0;
-    strandStatusReg = 0;
+    //This is set this way in Legion for some reason
+    strandStatusReg = 0x50000;
     fsr = 0;
 
     priContext = 0;
@@ -360,7 +367,7 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val)
           tba = val & ULL(~0x7FFF);
           break;
         case MISCREG_PSTATE:
-          pstate = val;
+          pstate = (val & PSTATE_MASK);
           break;
         case MISCREG_TL:
           tl = val;
@@ -522,7 +529,7 @@ void MiscRegFile::setRegWithEffect(int miscReg,
           //Set up performance counting based on pcr value
           break;
         case MISCREG_PSTATE:
-          pstate = val;
+          pstate = val & PSTATE_MASK;
           return;
         case MISCREG_TL:
           tl = val;