1 files changed, 50 insertions, 43 deletions

diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index d52e3983f..50a4f4871 100644
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -50,19 +50,24 @@ class Checkpoint;
 string SparcISA::getMiscRegName(RegIndex index)
 {
     static::string miscRegName[NumMiscRegs] =
-        {"y", "ccr", "asi", "tick", "pc", "fprs", "pcr", "pic",
+        {/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic",
          "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
          "stick", "stick_cmpr",
          "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
-         "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
-         "wstate", "gl",
+         "pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin",
+         "wstate",*/ "gl",
          "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
          "hstick_cmpr",
          "fsr"};
     return miscRegName[index];
 }
 
-void MiscRegFile::reset()
+enum RegMask
+{
+        PSTATE_MASK = (((1 << 4) - 1) << 1) | (((1 << 4) - 1) << 6) | (1 << 12)
+};
+
+void MiscRegFile::clear()
 {
     y = 0;
     ccr = 0;
@@ -88,12 +93,14 @@ void MiscRegFile::reset()
     otherwin = 0;
     wstate = 0;
     gl = 0;
-    hpstate = 0;
+    //In a T1, bit 11 is apparently always 1
+    hpstate = (1 << 11);
     memset(htstate, 0, sizeof(htstate));
     hintp = 0;
     htba = 0;
     hstick_cmpr = 0;
-    strandStatusReg = 0;
+    //This is set this way in Legion for some reason
+    strandStatusReg = 0x50000;
     fsr = 0;
     implicitInstAsi = ASI_PRIMARY;
     implicitDataAsi = ASI_PRIMARY;
@@ -102,10 +109,10 @@ void MiscRegFile::reset()
 MiscReg MiscRegFile::readReg(int miscReg)
 {
     switch (miscReg) {
-        case MISCREG_Y:
-          return y;
-        case MISCREG_CCR:
-          return ccr;
+//        case MISCREG_Y:
+//          return y;
+//        case MISCREG_CCR:
+//          return ccr;
         case MISCREG_ASI:
           return asi;
         case MISCREG_FPRS:
@@ -148,16 +155,16 @@ MiscReg MiscRegFile::readReg(int miscReg)
           return pil;
         case MISCREG_CWP:
           return cwp;
-        case MISCREG_CANSAVE:
-          return cansave;
-        case MISCREG_CANRESTORE:
-          return canrestore;
-        case MISCREG_CLEANWIN:
-          return cleanwin;
-        case MISCREG_OTHERWIN:
-          return otherwin;
-        case MISCREG_WSTATE:
-          return wstate;
+//        case MISCREG_CANSAVE:
+//          return cansave;
+//        case MISCREG_CANRESTORE:
+//          return canrestore;
+//        case MISCREG_CLEANWIN:
+//          return cleanwin;
+//        case MISCREG_OTHERWIN:
+//          return otherwin;
+//        case MISCREG_WSTATE:
+//          return wstate;
         case MISCREG_GL:
           return gl;
 
@@ -218,12 +225,12 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
 void MiscRegFile::setReg(int miscReg, const MiscReg &val)
 {
     switch (miscReg) {
-        case MISCREG_Y:
-          y = val;
-          break;
-        case MISCREG_CCR:
-          ccr = val;
-          break;
+//        case MISCREG_Y:
+//          y = val;
+//	  break;
+//        case MISCREG_CCR:
+//          ccr = val;
+//	  break;
         case MISCREG_ASI:
           asi = val;
           break;
@@ -273,7 +280,7 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val)
           tba = val & ULL(~0x7FFF);
           break;
         case MISCREG_PSTATE:
-          pstate = val;
+          pstate = (val & PSTATE_MASK);
           break;
         case MISCREG_TL:
           tl = val;
@@ -284,21 +291,21 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val)
         case MISCREG_CWP:
           cwp = val;
           break;
-        case MISCREG_CANSAVE:
-          cansave = val;
-          break;
-        case MISCREG_CANRESTORE:
-          canrestore = val;
-          break;
-        case MISCREG_CLEANWIN:
-          cleanwin = val;
-          break;
-        case MISCREG_OTHERWIN:
-          otherwin = val;
-          break;
-        case MISCREG_WSTATE:
-          wstate = val;
-          break;
+//        case MISCREG_CANSAVE:
+//          cansave = val;
+//	  break;
+//        case MISCREG_CANRESTORE:
+//          canrestore = val;
+//	  break;
+//        case MISCREG_CLEANWIN:
+//          cleanwin = val;
+//	  break;
+//        case MISCREG_OTHERWIN:
+//          otherwin = val;
+//	  break;
+//        case MISCREG_WSTATE:
+//          wstate = val;
+//	  break;
         case MISCREG_GL:
           gl = val;
           break;
@@ -375,7 +382,7 @@ void MiscRegFile::setRegWithEffect(int miscReg,
           //Set up performance counting based on pcr value
           break;
         case MISCREG_PSTATE:
-          pstate = val;
+          pstate = val & PSTATE_MASK;
           setImplicitAsis();
           return;
         case MISCREG_TL: