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-rw-r--r--src/arch/sparc/miscregfile.hh5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh
index 66c9f17df..ac0e930c5 100644
--- a/src/arch/sparc/miscregfile.hh
+++ b/src/arch/sparc/miscregfile.hh
@@ -39,6 +39,8 @@
#include <string>
+class Checkpoint;
+
namespace SparcISA
{
//These functions map register indices to names
@@ -259,6 +261,9 @@ namespace SparcISA
ThreadContext *tc);
MiscReg readFSRegWithEffect(int miscReg, ThreadContext * tc);
+ // Update interrupt state on softint or pil change
+ void checkSoftInt(ThreadContext *tc);
+
/** Process a tick compare event and generate an interrupt on the cpu if
* appropriate. */
void processTickCompare(ThreadContext *tc);