diff options
Diffstat (limited to 'src/arch/sparc/tlb.cc')
-rw-r--r-- | src/arch/sparc/tlb.cc | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 3ab40ce63..3ac3e5c9c 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -31,6 +31,7 @@ #include "arch/sparc/asi.hh" #include "arch/sparc/miscregfile.hh" #include "arch/sparc/tlb.hh" +#include "base/bitfield.hh" #include "base/trace.hh" #include "cpu/thread_context.hh" #include "cpu/base.hh" @@ -479,11 +480,15 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) panic("Twin ASIs not supported\n"); if (AsiIsPartialStore(asi)) panic("Partial Store ASIs not supported\n"); + if (AsiIsInterrupt(asi)) + panic("Interrupt ASIs not supported\n"); if (AsiIsMmu(asi)) goto handleMmuRegAccess; if (AsiIsScratchPad(asi)) goto handleScratchRegAccess; + if (AsiIsQueue(asi)) + goto handleQueueRegAccess; if (!AsiIsReal(asi) && !AsiIsNucleus(asi)) panic("Accessing ASI %#X. Should we?\n", asi); @@ -542,6 +547,20 @@ handleScratchRegAccess: writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); return new DataAccessException; } + goto regAccessOk; + +handleQueueRegAccess: + if (!priv && !hpriv) { + writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); + return new PrivilegedAction; + } + if (priv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) { + writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); + return new DataAccessException; + } + goto regAccessOk; + +regAccessOk: handleMmuRegAccess: DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); req->setMmapedIpr(true); @@ -575,6 +594,10 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) goto doMmuReadError; } break; + case ASI_QUEUE: + pkt->set(tc->readMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD + + (va >> 4) - 0x3c)); + break; case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: assert(va == 0); pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0)); @@ -672,6 +695,11 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) goto doMmuWriteError; } break; + case ASI_QUEUE: + assert(mbits(va,13,6) == va); + tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD + + (va >> 4) - 0x3c, data); + break; case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: assert(va == 0); tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data); |