diff options
Diffstat (limited to 'src/arch/sparc/tlb.cc')
-rw-r--r-- | src/arch/sparc/tlb.cc | 24 |
1 files changed, 8 insertions, 16 deletions
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 51eb83ac2..997bfe991 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -849,13 +849,6 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc, } Fault -TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) -{ - panic("Not implemented\n"); - return NoFault; -} - -Fault TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const { return NoFault; @@ -871,7 +864,7 @@ TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt) DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n", (uint32_t)pkt->req->getArchFlags(), pkt->getAddr()); - TLB *itb = tc->getITBPtr(); + TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr()); switch (asi) { case ASI_LSU_CONTROL_REG: @@ -1067,7 +1060,7 @@ TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n", (uint32_t)asi, va, data); - TLB *itb = tc->getITBPtr(); + TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr()); switch (asi) { case ASI_LSU_CONTROL_REG: @@ -1171,8 +1164,8 @@ TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) real_insert = bits(va, 9,9); pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : PageTableEntry::sun4u); - tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert, - pte, entry_insert); + itb->insert(va_insert, part_insert, ct_insert, real_insert, + pte, entry_insert); break; case ASI_DTLB_DATA_ACCESS_REG: entry_insert = bits(va, 8,3); @@ -1209,15 +1202,14 @@ TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) switch (bits(va,7,6)) { case 0: // demap page if (!ignore) - tc->getITBPtr()->demapPage(mbits(va,63,13), part_id, - bits(va,9,9), ctx_id); + itb->demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id); break; case 1: // demap context if (!ignore) - tc->getITBPtr()->demapContext(part_id, ctx_id); + itb->demapContext(part_id, ctx_id); break; case 2: - tc->getITBPtr()->demapAll(part_id); + itb->demapAll(part_id); break; default: panic("Invalid type for IMMU demap\n"); @@ -1303,7 +1295,7 @@ void TLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs) { uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0); - TLB * itb = tc->getITBPtr(); + TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr()); ptrs[0] = MakeTsbPtr(Ps0, tag_access, c0_tsb_ps0, c0_config, |