diff options
Diffstat (limited to 'src/arch/sparc/tlb.cc')
| -rw-r--r-- | src/arch/sparc/tlb.cc | 33 |
1 files changed, 15 insertions, 18 deletions
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index ddc37cf3b..a6179e0f8 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -42,6 +42,7 @@ #include "debug/TLB.hh" #include "mem/packet_access.hh" #include "mem/request.hh" +#include "sim/full_system.hh" #include "sim/system.hh" /* @todo remove some of the magic constants. -- ali @@ -497,14 +498,14 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc) if (e == NULL || !e->valid) { writeTagAccess(vaddr, context); - if (real) + if (real) { return new InstructionRealTranslationMiss; - else -#if FULL_SYSTEM - return new FastInstructionAccessMMUMiss; -#else - return new FastInstructionAccessMMUMiss(req->getVaddr()); -#endif + } else { + if (FullSystem) + return new FastInstructionAccessMMUMiss; + else + return new FastInstructionAccessMMUMiss(req->getVaddr()); + } } // were not priviledged accesing priv page @@ -709,14 +710,14 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write) if (e == NULL || !e->valid) { writeTagAccess(vaddr, context); DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); - if (real) + if (real) { return new DataRealTranslationMiss; - else -#if FULL_SYSTEM - return new FastDataAccessMMUMiss; -#else - return new FastDataAccessMMUMiss(req->getVaddr()); -#endif + } else { + if (FullSystem) + return new FastDataAccessMMUMiss; + else + return new FastDataAccessMMUMiss(req->getVaddr()); + } } @@ -840,8 +841,6 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc, translation->finish(translateAtomic(req, tc, mode), req, tc, mode); } -#if FULL_SYSTEM - Tick TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt) { @@ -1280,8 +1279,6 @@ doMmuWriteError: return tc->getCpuPtr()->ticks(1); } -#endif - void TLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs) { |